Interface design of high speed ADC based on FPGA
With the continuous improvement of communication technology, the data transmission rate is increasing rapidly. At present, many high-speed application scenarios such as 5G communication, automatic driving, radar, aerospace, and high-precision instrumentation are eager for more high-speed and stable...
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| Other Authors: | |
| Format: | Thesis-Master by Coursework |
| Language: | English |
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Nanyang Technological University
2023
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| Online Access: | https://hdl.handle.net/10356/168002 |
| _version_ | 1811693048952782848 |
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| author | Li, Ziyi |
| author2 | Zheng Yuanjin |
| author_facet | Zheng Yuanjin Li, Ziyi |
| author_sort | Li, Ziyi |
| collection | NTU |
| description | With the continuous improvement of communication technology, the data transmission rate is increasing rapidly. At present, many high-speed application scenarios such as 5G communication, automatic driving, radar, aerospace, and high-precision instrumentation are eager for more high-speed and stable serial data interfaces. In order to meet the needs of data-intensive applications to process data faster, experts and scholars from various countries have begun to use various methods to study it.
This dissertation designs the interface of high-speed ADC based on FPGA, and proposes a digital IP module for pulse data detection and clock domain transmission, which can effectively read the data of high-speed ADC more stably and accurately, and achieved relatively good results in actual simulation and testing. |
| first_indexed | 2024-10-01T06:45:29Z |
| format | Thesis-Master by Coursework |
| id | ntu-10356/168002 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:45:29Z |
| publishDate | 2023 |
| publisher | Nanyang Technological University |
| record_format | dspace |
| spelling | ntu-10356/1680022023-07-04T15:14:51Z Interface design of high speed ADC based on FPGA Li, Ziyi Zheng Yuanjin School of Electrical and Electronic Engineering YJZHENG@ntu.edu.sg Engineering::Electrical and electronic engineering With the continuous improvement of communication technology, the data transmission rate is increasing rapidly. At present, many high-speed application scenarios such as 5G communication, automatic driving, radar, aerospace, and high-precision instrumentation are eager for more high-speed and stable serial data interfaces. In order to meet the needs of data-intensive applications to process data faster, experts and scholars from various countries have begun to use various methods to study it. This dissertation designs the interface of high-speed ADC based on FPGA, and proposes a digital IP module for pulse data detection and clock domain transmission, which can effectively read the data of high-speed ADC more stably and accurately, and achieved relatively good results in actual simulation and testing. Master of Science (Electronics) 2023-05-21T08:47:49Z 2023-05-21T08:47:49Z 2023 Thesis-Master by Coursework Li, Z. (2023). Interface design of high speed ADC based on FPGA. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/168002 https://hdl.handle.net/10356/168002 en application/pdf Nanyang Technological University |
| spellingShingle | Engineering::Electrical and electronic engineering Li, Ziyi Interface design of high speed ADC based on FPGA |
| title | Interface design of high speed ADC based on FPGA |
| title_full | Interface design of high speed ADC based on FPGA |
| title_fullStr | Interface design of high speed ADC based on FPGA |
| title_full_unstemmed | Interface design of high speed ADC based on FPGA |
| title_short | Interface design of high speed ADC based on FPGA |
| title_sort | interface design of high speed adc based on fpga |
| topic | Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/168002 |
| work_keys_str_mv | AT liziyi interfacedesignofhighspeedadcbasedonfpga |