Ternary full adder designs employing unary operators and ternary multiplexers
The design of the Ternary Full Adders (TFA) employing Carbon Nanotube Field-Effect Transistors (CNFET) has been widely presented in the literature. To obtain the optimal design of these ternary adders, we propose two new different designs, TFA1 with 59 CNFETs and TFA2 with 55 CNFETs, that use unary...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2023
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/169232 |
| _version_ | 1811689275311259648 |
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| author | Jaber, Ramzi A. Haidar, Ali M. Kassem, Abdallah Zahoor, Furqan |
| author2 | School of Computer Science and Engineering |
| author_facet | School of Computer Science and Engineering Jaber, Ramzi A. Haidar, Ali M. Kassem, Abdallah Zahoor, Furqan |
| author_sort | Jaber, Ramzi A. |
| collection | NTU |
| description | The design of the Ternary Full Adders (TFA) employing Carbon Nanotube Field-Effect Transistors (CNFET) has been widely presented in the literature. To obtain the optimal design of these ternary adders, we propose two new different designs, TFA1 with 59 CNFETs and TFA2 with 55 CNFETs, that use unary operator gates with two voltage supplies (Vdd and Vdd/2) to reduce the transistor count and energy consumption. In addition, this paper proposes two 4-trit Ripple Carry Adders (RCA) based on the two proposed TFA1 and TFA2; we use the HSPICE simulator and 32 nm CNFET to simulate the proposed circuits under different voltages, temperatures, and output loads. The simulation results show the improvements of the designs in a reduction of over 41% in energy consumption (PDP), and over 64% in Energy Delay Product (EDP) compared to the best recent works in the literature. |
| first_indexed | 2024-10-01T05:45:31Z |
| format | Journal Article |
| id | ntu-10356/169232 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:45:31Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | ntu-10356/1692322023-07-14T15:35:51Z Ternary full adder designs employing unary operators and ternary multiplexers Jaber, Ramzi A. Haidar, Ali M. Kassem, Abdallah Zahoor, Furqan School of Computer Science and Engineering Engineering::Computer science and engineering Logic Design Nanoscale Devices The design of the Ternary Full Adders (TFA) employing Carbon Nanotube Field-Effect Transistors (CNFET) has been widely presented in the literature. To obtain the optimal design of these ternary adders, we propose two new different designs, TFA1 with 59 CNFETs and TFA2 with 55 CNFETs, that use unary operator gates with two voltage supplies (Vdd and Vdd/2) to reduce the transistor count and energy consumption. In addition, this paper proposes two 4-trit Ripple Carry Adders (RCA) based on the two proposed TFA1 and TFA2; we use the HSPICE simulator and 32 nm CNFET to simulate the proposed circuits under different voltages, temperatures, and output loads. The simulation results show the improvements of the designs in a reduction of over 41% in energy consumption (PDP), and over 64% in Energy Delay Product (EDP) compared to the best recent works in the literature. Published version 2023-07-10T02:31:08Z 2023-07-10T02:31:08Z 2023 Journal Article Jaber, R. A., Haidar, A. M., Kassem, A. & Zahoor, F. (2023). Ternary full adder designs employing unary operators and ternary multiplexers. Micromachines, 14(5), 1064-. https://dx.doi.org/10.3390/mi14051064 2072-666X https://hdl.handle.net/10356/169232 10.3390/mi14051064 37241687 2-s2.0-85160589149 5 14 1064 en Micromachines © 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/). application/pdf |
| spellingShingle | Engineering::Computer science and engineering Logic Design Nanoscale Devices Jaber, Ramzi A. Haidar, Ali M. Kassem, Abdallah Zahoor, Furqan Ternary full adder designs employing unary operators and ternary multiplexers |
| title | Ternary full adder designs employing unary operators and ternary multiplexers |
| title_full | Ternary full adder designs employing unary operators and ternary multiplexers |
| title_fullStr | Ternary full adder designs employing unary operators and ternary multiplexers |
| title_full_unstemmed | Ternary full adder designs employing unary operators and ternary multiplexers |
| title_short | Ternary full adder designs employing unary operators and ternary multiplexers |
| title_sort | ternary full adder designs employing unary operators and ternary multiplexers |
| topic | Engineering::Computer science and engineering Logic Design Nanoscale Devices |
| url | https://hdl.handle.net/10356/169232 |
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