Ultra-high-speed accelerator architecture for convolutional neural network based on processing-in-memory using resistive random access memory
Processing-in-Memory (PIM) based on Resistive Random Access Memory (RRAM) is an emerging acceleration architecture for artificial neural networks. This paper proposes an RRAM PIM accelerator architecture that does not use Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs). A...
| Main Authors: | , , , , , , , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2023
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/169464 |
| _version_ | 1824455800108613632 |
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| author | Wang, Hongzhe Wang, Junjie Hu, Hao Li, Guo Hu, Shaogang Yu, Qi Liu, Zhen Chen, Tupei Zhou, Shijie Liu, Yang |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Wang, Hongzhe Wang, Junjie Hu, Hao Li, Guo Hu, Shaogang Yu, Qi Liu, Zhen Chen, Tupei Zhou, Shijie Liu, Yang |
| author_sort | Wang, Hongzhe |
| collection | NTU |
| description | Processing-in-Memory (PIM) based on Resistive Random Access Memory (RRAM) is an emerging acceleration architecture for artificial neural networks. This paper proposes an RRAM PIM accelerator architecture that does not use Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs). Additionally, no additional memory usage is required to avoid the need for a large amount of data transportation in convolution computation. Partial quantization is introduced to reduce the accuracy loss. The proposed architecture can substantially reduce the overall power consumption and accelerate computation. The simulation results show that the image recognition rate for the Convolutional Neural Network (CNN) algorithm can reach 284 frames per second at 50 MHz using this architecture. The accuracy of the partial quantization remains almost unchanged compared to the algorithm without quantization. |
| first_indexed | 2025-02-19T03:43:57Z |
| format | Journal Article |
| id | ntu-10356/169464 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2025-02-19T03:43:57Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | ntu-10356/1694642023-07-21T15:40:30Z Ultra-high-speed accelerator architecture for convolutional neural network based on processing-in-memory using resistive random access memory Wang, Hongzhe Wang, Junjie Hu, Hao Li, Guo Hu, Shaogang Yu, Qi Liu, Zhen Chen, Tupei Zhou, Shijie Liu, Yang School of Electrical and Electronic Engineering Engineering::Electrical and electronic engineering RRAM Convolutional Neural Network Processing-in-Memory (PIM) based on Resistive Random Access Memory (RRAM) is an emerging acceleration architecture for artificial neural networks. This paper proposes an RRAM PIM accelerator architecture that does not use Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs). Additionally, no additional memory usage is required to avoid the need for a large amount of data transportation in convolution computation. Partial quantization is introduced to reduce the accuracy loss. The proposed architecture can substantially reduce the overall power consumption and accelerate computation. The simulation results show that the image recognition rate for the Convolutional Neural Network (CNN) algorithm can reach 284 frames per second at 50 MHz using this architecture. The accuracy of the partial quantization remains almost unchanged compared to the algorithm without quantization. Published version This work is financially supported by NSFC under project No 92064004. 2023-07-19T06:29:50Z 2023-07-19T06:29:50Z 2023 Journal Article Wang, H., Wang, J., Hu, H., Li, G., Hu, S., Yu, Q., Liu, Z., Chen, T., Zhou, S. & Liu, Y. (2023). Ultra-high-speed accelerator architecture for convolutional neural network based on processing-in-memory using resistive random access memory. Sensors, 23(5), 2401-. https://dx.doi.org/10.3390/s23052401 1424-8220 https://hdl.handle.net/10356/169464 10.3390/s23052401 36904605 2-s2.0-85150170421 5 23 2401 en Sensors © 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/). application/pdf |
| spellingShingle | Engineering::Electrical and electronic engineering RRAM Convolutional Neural Network Wang, Hongzhe Wang, Junjie Hu, Hao Li, Guo Hu, Shaogang Yu, Qi Liu, Zhen Chen, Tupei Zhou, Shijie Liu, Yang Ultra-high-speed accelerator architecture for convolutional neural network based on processing-in-memory using resistive random access memory |
| title | Ultra-high-speed accelerator architecture for convolutional neural network based on processing-in-memory using resistive random access memory |
| title_full | Ultra-high-speed accelerator architecture for convolutional neural network based on processing-in-memory using resistive random access memory |
| title_fullStr | Ultra-high-speed accelerator architecture for convolutional neural network based on processing-in-memory using resistive random access memory |
| title_full_unstemmed | Ultra-high-speed accelerator architecture for convolutional neural network based on processing-in-memory using resistive random access memory |
| title_short | Ultra-high-speed accelerator architecture for convolutional neural network based on processing-in-memory using resistive random access memory |
| title_sort | ultra high speed accelerator architecture for convolutional neural network based on processing in memory using resistive random access memory |
| topic | Engineering::Electrical and electronic engineering RRAM Convolutional Neural Network |
| url | https://hdl.handle.net/10356/169464 |
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