Transposable 9T-SRAM computation-in-memory for on-chip learning with probability-based single-slope SAR hybrid ADC for edge devices

Transposable 9T-SRAM computation-in-memory for on-chip learning with probability-based single-slope SAR hybrid ADC for edge devices

This letter proposes a two-way transposable SRAM computation-in-memory (CIM) macro for inference and training in convolutional neural networks (CNNs). A novel 9T SRAM bit-cell conducts local two-way computing without shared processing units, achieving higher-processing throughput from every bit-cell...

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Bibliographic Details
Main Authors: Jo, Yong-Jun, Zhang, Xin, Liu, Jiahao, Zhou, Jun, Zheng, Yuanjin, Kim, Tony Tae-Hyoung
Other Authors: School of Electrical and Electronic Engineering
Format: Journal Article
Language:English
Published: 2023
Subjects:
Engineering::Electrical and electronic engineering
On-Chip Learning
Zero-Skip
Online Access:https://hdl.handle.net/10356/170098

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