A monotonic early output asynchronous full adder
This article introduces a novel asynchronous full adder that operates in an input–output mode (IOM), displaying both monotonicity and an early output characteristic. In a monotonic asynchronous circuit, the intermediate and primary outputs exhibit similar signal transitions as the primary inputs dur...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2023
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| Online Access: | https://hdl.handle.net/10356/170513 |
| _version_ | 1826130015563022336 |
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| author | Balasubramanian, Padmanabhan Maskell, Douglas L. |
| author2 | School of Computer Science and Engineering |
| author_facet | School of Computer Science and Engineering Balasubramanian, Padmanabhan Maskell, Douglas L. |
| author_sort | Balasubramanian, Padmanabhan |
| collection | NTU |
| description | This article introduces a novel asynchronous full adder that operates in an input–output mode (IOM), displaying both monotonicity and an early output characteristic. In a monotonic asynchronous circuit, the intermediate and primary outputs exhibit similar signal transitions as the primary inputs during data and spacer application. The proposed asynchronous full adder ensures monotonicity for processing data and spacer, utilizing dual-rail encoding for inputs and outputs, and corresponds to return-to-zero (RtZ) and return-to-one (RtO) handshaking. The early output feature of the proposed full adder allows the production of sum and carry outputs based on the adder inputs regardless of the carry input when the spacer is supplied. When utilized in a ripple carry adder (RCA) architecture, the proposed full adder achieves significant reductions in design metrics, such as cycle time, area, and power, compared to existing IOM asynchronous full adders. For a 32-bit RCA implementation using a 28 nm CMOS technology, the proposed full adder outperforms an existing state-of-the-art high-speed asynchronous full adder by reducing the cycle time by 10.4% and the area by 15.8% for RtZ handshaking and reduces the cycle time by 9.8% and the area by 15.8% for RtO handshaking without incurring any power penalty. Further, in terms of the power-cycle time product, which serves as a representative measure of energy, the proposed full adder yields an 11.8% reduction for RtZ handshaking and an 11.2% reduction for RtO handshaking. |
| first_indexed | 2024-10-01T07:49:39Z |
| format | Journal Article |
| id | ntu-10356/170513 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T07:49:39Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | ntu-10356/1705132023-09-22T15:35:56Z A monotonic early output asynchronous full adder Balasubramanian, Padmanabhan Maskell, Douglas L. School of Computer Science and Engineering Hardware & Embedded Systems Lab (HESL) Engineering::Electrical and electronic engineering::Computer hardware, software and systems Engineering::Electrical and electronic engineering::Integrated circuits Engineering::Electrical and electronic engineering::Electronic circuits Engineering::Computer science and engineering::Hardware Digital Logic Design Arithmetic Circuits Asynchronous Circuits Digital Circuits Low Power Design This article introduces a novel asynchronous full adder that operates in an input–output mode (IOM), displaying both monotonicity and an early output characteristic. In a monotonic asynchronous circuit, the intermediate and primary outputs exhibit similar signal transitions as the primary inputs during data and spacer application. The proposed asynchronous full adder ensures monotonicity for processing data and spacer, utilizing dual-rail encoding for inputs and outputs, and corresponds to return-to-zero (RtZ) and return-to-one (RtO) handshaking. The early output feature of the proposed full adder allows the production of sum and carry outputs based on the adder inputs regardless of the carry input when the spacer is supplied. When utilized in a ripple carry adder (RCA) architecture, the proposed full adder achieves significant reductions in design metrics, such as cycle time, area, and power, compared to existing IOM asynchronous full adders. For a 32-bit RCA implementation using a 28 nm CMOS technology, the proposed full adder outperforms an existing state-of-the-art high-speed asynchronous full adder by reducing the cycle time by 10.4% and the area by 15.8% for RtZ handshaking and reduces the cycle time by 9.8% and the area by 15.8% for RtO handshaking without incurring any power penalty. Further, in terms of the power-cycle time product, which serves as a representative measure of energy, the proposed full adder yields an 11.8% reduction for RtZ handshaking and an 11.2% reduction for RtO handshaking. Ministry of Education (MOE) Published version This research was partially funded by the Singapore Ministry of Education (MOE), Academic Research Fund under grant numbers Tier-1 RG48/21 and Tier-1 RG127/22. 2023-09-19T01:46:00Z 2023-09-19T01:46:00Z 2023 Journal Article Balasubramanian, P. & Maskell, D. L. (2023). A monotonic early output asynchronous full adder. Technologies, 11(5), 126-. https://dx.doi.org/10.3390/technologies11050126 2227-7080 https://hdl.handle.net/10356/170513 10.3390/technologies11050126 5 11 126 en RG48/21 RG127/22 Technologies © 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/). application/pdf |
| spellingShingle | Engineering::Electrical and electronic engineering::Computer hardware, software and systems Engineering::Electrical and electronic engineering::Integrated circuits Engineering::Electrical and electronic engineering::Electronic circuits Engineering::Computer science and engineering::Hardware Digital Logic Design Arithmetic Circuits Asynchronous Circuits Digital Circuits Low Power Design Balasubramanian, Padmanabhan Maskell, Douglas L. A monotonic early output asynchronous full adder |
| title | A monotonic early output asynchronous full adder |
| title_full | A monotonic early output asynchronous full adder |
| title_fullStr | A monotonic early output asynchronous full adder |
| title_full_unstemmed | A monotonic early output asynchronous full adder |
| title_short | A monotonic early output asynchronous full adder |
| title_sort | monotonic early output asynchronous full adder |
| topic | Engineering::Electrical and electronic engineering::Computer hardware, software and systems Engineering::Electrical and electronic engineering::Integrated circuits Engineering::Electrical and electronic engineering::Electronic circuits Engineering::Computer science and engineering::Hardware Digital Logic Design Arithmetic Circuits Asynchronous Circuits Digital Circuits Low Power Design |
| url | https://hdl.handle.net/10356/170513 |
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