High-speed and energy-efficient asynchronous carry look-ahead adder
Addition is a fundamental computer arithmetic operation that is widely performed in microprocessors, digital signal processors, and application-specific processors. The design of a high-speed and energy-efficient adder is thus useful and important for practical applications. In this context, this pa...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2023
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| Online Access: | https://hdl.handle.net/10356/170903 |
| _version_ | 1811685564994289664 |
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| author | Balasubramanian, Padmanabhan Liu, Weichen |
| author2 | School of Computer Science and Engineering |
| author_facet | School of Computer Science and Engineering Balasubramanian, Padmanabhan Liu, Weichen |
| author_sort | Balasubramanian, Padmanabhan |
| collection | NTU |
| description | Addition is a fundamental computer arithmetic operation that is widely performed in microprocessors, digital signal processors, and application-specific processors. The design of a high-speed and energy-efficient adder is thus useful and important for practical applications. In this context, this paper presents the designs of novel asynchronous carry look-ahead adders (CLAs) viz. a standard CLA (SCLA) and a block CLA (BCLA). The proposed CLAs are monotonic, dual-rail encoded, and are realized according to return-to-zero handshake (RZH) and return-to-one handshake (ROH) protocols using a 28-nm CMOS process technology. The proposed BCLA has a slight edge over the proposed SCLA, and the proposed BCLA reports the following optimizations in design metrics such as cycle time (delay), area, and power compared to a recently presented state-of-the-art asynchronous CLA for a 32-bit addition: (i) 32.6% reduction in cycle time, 29% reduction in area, 4.3% reduction in power, and 35.5% reduction in energy for RZH, and (ii) 31.4% reduction in cycle time, 28.9% reduction in area, 4.4% reduction in power, and 34.4% reduction in energy for ROH. Also, the proposed BCLA reports reductions in cycle time and power/energy compared to many other asynchronous adders. |
| first_indexed | 2024-10-01T04:46:32Z |
| format | Journal Article |
| id | ntu-10356/170903 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:46:32Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | ntu-10356/1709032023-10-13T15:36:37Z High-speed and energy-efficient asynchronous carry look-ahead adder Balasubramanian, Padmanabhan Liu, Weichen School of Computer Science and Engineering Engineering::Computer science and engineering::Hardware Engineering::Electrical and electronic engineering::Integrated circuits Asynchronous Circuits Arithmetic Circuits Digital Logic Design Digital Circuits Low Power Design Addition is a fundamental computer arithmetic operation that is widely performed in microprocessors, digital signal processors, and application-specific processors. The design of a high-speed and energy-efficient adder is thus useful and important for practical applications. In this context, this paper presents the designs of novel asynchronous carry look-ahead adders (CLAs) viz. a standard CLA (SCLA) and a block CLA (BCLA). The proposed CLAs are monotonic, dual-rail encoded, and are realized according to return-to-zero handshake (RZH) and return-to-one handshake (ROH) protocols using a 28-nm CMOS process technology. The proposed BCLA has a slight edge over the proposed SCLA, and the proposed BCLA reports the following optimizations in design metrics such as cycle time (delay), area, and power compared to a recently presented state-of-the-art asynchronous CLA for a 32-bit addition: (i) 32.6% reduction in cycle time, 29% reduction in area, 4.3% reduction in power, and 35.5% reduction in energy for RZH, and (ii) 31.4% reduction in cycle time, 28.9% reduction in area, 4.4% reduction in power, and 34.4% reduction in energy for ROH. Also, the proposed BCLA reports reductions in cycle time and power/energy compared to many other asynchronous adders. Ministry of Education (MOE) Nanyang Technological University Published version This work is partially supported by the Ministry of Education, Singapore, under its Academic Research Fund Tier 2 grant (MOE2019-T2-1-071), and Nanyang Technological University, Singapore, under its NAP grant (M4082282). 2023-10-11T06:45:19Z 2023-10-11T06:45:19Z 2023 Journal Article Balasubramanian, P. & Liu, W. (2023). High-speed and energy-efficient asynchronous carry look-ahead adder. PLOS ONE, 18(10), e0289569-. https://dx.doi.org/10.1371/journal.pone.0289569 1932-6203 https://hdl.handle.net/10356/170903 10.1371/journal.pone.0289569 37796887 10 18 e0289569 en MOE2019-T2-1-071 NAP (M4082282) PLOS ONE © 2023 Balasubramanian, Liu. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited. application/pdf |
| spellingShingle | Engineering::Computer science and engineering::Hardware Engineering::Electrical and electronic engineering::Integrated circuits Asynchronous Circuits Arithmetic Circuits Digital Logic Design Digital Circuits Low Power Design Balasubramanian, Padmanabhan Liu, Weichen High-speed and energy-efficient asynchronous carry look-ahead adder |
| title | High-speed and energy-efficient asynchronous carry look-ahead adder |
| title_full | High-speed and energy-efficient asynchronous carry look-ahead adder |
| title_fullStr | High-speed and energy-efficient asynchronous carry look-ahead adder |
| title_full_unstemmed | High-speed and energy-efficient asynchronous carry look-ahead adder |
| title_short | High-speed and energy-efficient asynchronous carry look-ahead adder |
| title_sort | high speed and energy efficient asynchronous carry look ahead adder |
| topic | Engineering::Computer science and engineering::Hardware Engineering::Electrical and electronic engineering::Integrated circuits Asynchronous Circuits Arithmetic Circuits Digital Logic Design Digital Circuits Low Power Design |
| url | https://hdl.handle.net/10356/170903 |
| work_keys_str_mv | AT balasubramanianpadmanabhan highspeedandenergyefficientasynchronouscarrylookaheadadder AT liuweichen highspeedandenergyefficientasynchronouscarrylookaheadadder |