Mo, Z., & Puiu, P. D. (2023). Investigation of a modified NPN transistor in CMOS structures for enhanced ESD-induced latch-up protection. Nanyang Technological University.
Chicago Style (17th ed.) CitationMo, Zhiyuan, and Poenar Daniel Puiu. Investigation of a Modified NPN Transistor in CMOS Structures for Enhanced ESD-induced Latch-up Protection. Nanyang Technological University, 2023.
MLA (9th ed.) CitationMo, Zhiyuan, and Poenar Daniel Puiu. Investigation of a Modified NPN Transistor in CMOS Structures for Enhanced ESD-induced Latch-up Protection. Nanyang Technological University, 2023.
Warning: These citations may not always be 100% accurate.