Investigation of a modified NPN transistor in CMOS structures for enhanced ESD-induced latch-up protection
Integrated circuits (ICs) are vital in modern electronics, including everyday life, industrial manufacturing and military equipment. Reducing transistor size and improving performance requires shrinking the gate oxide layer, which makes ICs more fragile and vulnerable to electrostatic discharg...
| 主要作者: | |
|---|---|
| 其他作者: | |
| 格式: | Thesis-Master by Coursework |
| 语言: | English |
| 出版: |
Nanyang Technological University
2023
|
| 主题: | |
| 在线阅读: | https://hdl.handle.net/10356/172084 |