Design of capacitorless LDO with compensation circuits
This project proposes two solutions to the present bulky external capacitor low-dropout voltage regulators (LDO). The large output capacitor is reduced allowing for greater power system integration for system-on-chip (SoC) application, while the LDO system still maintains good stability by inserting...
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| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2009
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| Online Access: | http://hdl.handle.net/10356/17254 |
| _version_ | 1826122532623745024 |
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| author | Xiong, Yuanting. |
| author2 | Ng Lian Soon |
| author_facet | Ng Lian Soon Xiong, Yuanting. |
| author_sort | Xiong, Yuanting. |
| collection | NTU |
| description | This project proposes two solutions to the present bulky external capacitor low-dropout voltage regulators (LDO). The large output capacitor is reduced allowing for greater power system integration for system-on-chip (SoC) application, while the LDO system still maintains good stability by inserting the compensation circuit block. The capacitorless LDOs were fabricated in a commercial 0.18um CMOS technology with 100mA full load and 3V power supply. The two designed LDO systems are capable of regulating a 2.8V output voltage with output load of 50pF and 0pF respectively. The first proposed compensation circuit block makes use of a current amplifier. In this LDO proposal, the output voltage spike is reduced to as low as 200mV in a full load transient, the response time is shortened and the phase margin is optimized to 88.8 in the transient response. The second proposed compensation circuit block uses a buffer stage and a miller capacitor. The second LDO proposal has a 400mV voltage spike in a full load transient, and its phase margin is 65.6. The simulation results are obtained from the Cadence ADE Environment, only the typical model is measured. The layout of the first LDO is 0.1265 (0.557mm0.227mm). |
| first_indexed | 2024-10-01T05:50:01Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/17254 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:50:01Z |
| publishDate | 2009 |
| record_format | dspace |
| spelling | ntu-10356/172542023-07-07T16:51:13Z Design of capacitorless LDO with compensation circuits Xiong, Yuanting. Ng Lian Soon School of Electrical and Electronic Engineering Centre for Integrated Circuits and Systems DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits This project proposes two solutions to the present bulky external capacitor low-dropout voltage regulators (LDO). The large output capacitor is reduced allowing for greater power system integration for system-on-chip (SoC) application, while the LDO system still maintains good stability by inserting the compensation circuit block. The capacitorless LDOs were fabricated in a commercial 0.18um CMOS technology with 100mA full load and 3V power supply. The two designed LDO systems are capable of regulating a 2.8V output voltage with output load of 50pF and 0pF respectively. The first proposed compensation circuit block makes use of a current amplifier. In this LDO proposal, the output voltage spike is reduced to as low as 200mV in a full load transient, the response time is shortened and the phase margin is optimized to 88.8 in the transient response. The second proposed compensation circuit block uses a buffer stage and a miller capacitor. The second LDO proposal has a 400mV voltage spike in a full load transient, and its phase margin is 65.6. The simulation results are obtained from the Cadence ADE Environment, only the typical model is measured. The layout of the first LDO is 0.1265 (0.557mm0.227mm). Bachelor of Engineering 2009-06-04T07:17:36Z 2009-06-04T07:17:36Z 2009 2009 Final Year Project (FYP) http://hdl.handle.net/10356/17254 en Nanyang Technological University 106 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Xiong, Yuanting. Design of capacitorless LDO with compensation circuits |
| title | Design of capacitorless LDO with compensation circuits |
| title_full | Design of capacitorless LDO with compensation circuits |
| title_fullStr | Design of capacitorless LDO with compensation circuits |
| title_full_unstemmed | Design of capacitorless LDO with compensation circuits |
| title_short | Design of capacitorless LDO with compensation circuits |
| title_sort | design of capacitorless ldo with compensation circuits |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
| url | http://hdl.handle.net/10356/17254 |
| work_keys_str_mv | AT xiongyuanting designofcapacitorlessldowithcompensationcircuits |