Design of a 40nm CMOS transconductance amplifier for low-dropout regulator

Modern portable and high-performance electronic devices place higher limits on power consumption and space of the power management system. LDO (Low Dropout) regulator is an important part of the power management system to provide accurate and stable voltage output to the load device. This project pr...

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Bibliographic Details
Main Author: Jiang, Haochen
Other Authors: Chan Pak Kwong
Format: Thesis-Master by Coursework
Language:English
Published: Nanyang Technological University 2024
Subjects:
Online Access:https://hdl.handle.net/10356/173428
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author Jiang, Haochen
author2 Chan Pak Kwong
author_facet Chan Pak Kwong
Jiang, Haochen
author_sort Jiang, Haochen
collection NTU
description Modern portable and high-performance electronic devices place higher limits on power consumption and space of the power management system. LDO (Low Dropout) regulator is an important part of the power management system to provide accurate and stable voltage output to the load device. This project proposes a capacitorless LDO regulator design with dynamic cascode biasing transconductance amplifier based on TSMC 40nm process. A low impedance loading network with overshoot suppression is used to allow stable operation within a load between 0uA and 50mA. Simulation results show that the proposed LDO regulator has a quiescent current of 12.52μA at 0 load current, a maximum overshoot/undershoot of 90mV, and a settling time of less than 1.8μs. Compared to conventional transconductance amplifier based LDO regulator, it is faster by about 2.6 times and the maximum transient voltage variation is reduced by 141mV.
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spelling ntu-10356/1734282024-02-09T15:41:45Z Design of a 40nm CMOS transconductance amplifier for low-dropout regulator Jiang, Haochen Chan Pak Kwong School of Electrical and Electronic Engineering epkchan@ntu.edu.sg Engineering Modern portable and high-performance electronic devices place higher limits on power consumption and space of the power management system. LDO (Low Dropout) regulator is an important part of the power management system to provide accurate and stable voltage output to the load device. This project proposes a capacitorless LDO regulator design with dynamic cascode biasing transconductance amplifier based on TSMC 40nm process. A low impedance loading network with overshoot suppression is used to allow stable operation within a load between 0uA and 50mA. Simulation results show that the proposed LDO regulator has a quiescent current of 12.52μA at 0 load current, a maximum overshoot/undershoot of 90mV, and a settling time of less than 1.8μs. Compared to conventional transconductance amplifier based LDO regulator, it is faster by about 2.6 times and the maximum transient voltage variation is reduced by 141mV. Master's degree 2024-02-05T01:03:41Z 2024-02-05T01:03:41Z 2023 Thesis-Master by Coursework Jiang, H. (2023). Design of a 40nm CMOS transconductance amplifier for low-dropout regulator. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/173428 https://hdl.handle.net/10356/173428 en ISM-DISS-03637 application/pdf Nanyang Technological University
spellingShingle Engineering
Jiang, Haochen
Design of a 40nm CMOS transconductance amplifier for low-dropout regulator
title Design of a 40nm CMOS transconductance amplifier for low-dropout regulator
title_full Design of a 40nm CMOS transconductance amplifier for low-dropout regulator
title_fullStr Design of a 40nm CMOS transconductance amplifier for low-dropout regulator
title_full_unstemmed Design of a 40nm CMOS transconductance amplifier for low-dropout regulator
title_short Design of a 40nm CMOS transconductance amplifier for low-dropout regulator
title_sort design of a 40nm cmos transconductance amplifier for low dropout regulator
topic Engineering
url https://hdl.handle.net/10356/173428
work_keys_str_mv AT jianghaochen designofa40nmcmostransconductanceamplifierforlowdropoutregulator