CMOS-fabricated ring surface ion trap with TSV integration

CMOS-fabricated ring surface ion trap with TSV integration

We present the design, fabrication, and test of ring surface trap on 12-inch wafers with a CMOS process. The design is based on Through Silicon Vias (TSV) interconnects. Up to 200 ions were loaded and cooled; preliminary compensations of electrostatic potential imperfections show that rotational sym...

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Bibliographic Details
Main Authors: Zhao, Peng, Lim, Yu Dian, Li, Hong Yu, Likforman, Jean-Pierre, Guidoni, Luca, Desormeaux, Lilay Gros, Tan, Chuan Seng
Other Authors: School of Electrical and Electronic Engineering
Format: Conference Paper
Language:English
Published: 2024
Subjects:
Engineering
Fabrication
Electron traps
Online Access:https://hdl.handle.net/10356/175533

Internet

https://hdl.handle.net/10356/175533

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