Monotonic asynchronous two-bit full adder
Monotonic circuits are a class of input–output mode (IOM) asynchronous circuits that are relaxed compared to quasi-delay-insensitive (QDI) IOM asynchronous circuits in terms of signaling the completion of internal processing. Some recent works have demonstrated the superiority of monotonic logic ove...
| المؤلفون الرئيسيون: | , |
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| مؤلفون آخرون: | |
| التنسيق: | Journal Article |
| اللغة: | English |
| منشور في: |
2024
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| الموضوعات: | |
| الوصول للمادة أونلاين: | https://hdl.handle.net/10356/175653 |
| _version_ | 1826117673176530944 |
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| author | Balasubramanian, Padmanabhan Maskell, Douglas Leslie |
| author2 | School of Computer Science and Engineering |
| author_facet | School of Computer Science and Engineering Balasubramanian, Padmanabhan Maskell, Douglas Leslie |
| author_sort | Balasubramanian, Padmanabhan |
| collection | NTU |
| description | Monotonic circuits are a class of input–output mode (IOM) asynchronous circuits that are relaxed compared to quasi-delay-insensitive (QDI) IOM asynchronous circuits in terms of signaling the completion of internal processing. Some recent works have demonstrated the superiority of monotonic logic over QDI logic for arithmetic circuits such as adders and multipliers. This paper presents a new monotonic asynchronous two-bit full adder (TFA) that can be duplicated and cascaded to form a ripple-carry adder (RCA). While an RCA is a slow adder with respect to synchronous design, with respect to IOM asynchronous design an RCA is a noteworthy adder since it has perhaps the least reverse latency that is not attainable through other IOM asynchronous adders. Conventionally, an RCA is constructed via a cascade of one-bit full adders (OFAs). An OFA adds two input bits along with any carry input and produces a sum bit and any carry output. On the other hand, a TFA simultaneously adds two pairs of input bits along with any carry input and produces two sum bits and any carry output. Using our proposed monotonic TFA, we realized an RCA to compare its performance with RCAs constructed using different asynchronous OFAs, and RCAs constructed using existing TFAs. We considered the popular delay-insensitive dual-rail scheme for encoding the adder inputs and outputs, and two 4-phase handshake protocols, namely return-to-zero handshaking (R0H) and return-to-one handshaking (R1H) for communication separately. We used a 28 nm CMOS process for implementation and considered a 32-bit addition as an example. Based on the design metrics estimated, the following inferences were derived: (i) compared to the RCA using the state-of-the-art monotonic OFA, the RCA incorporating the proposed TFA achieved a 26% reduction in cycle time for R0H and a 28.5% reduction in cycle time for R1H while dissipating almost the same power; the cycle time governs the data application rate in an IOM asynchronous circuit, and (ii) compared to the RCA comprising an early output QDI TFA, the RCA incorporating the proposed TFA achieved a 22.3% reduction in cycle time for R0H and a 25.4% reduction in cycle time for R1H while dissipating moderately less power. Also, compared to the existing early output QDI TFA, the proposed TFA occupies 40.9% less area for R0H and 42% less area for R1H. |
| first_indexed | 2024-10-01T04:31:30Z |
| format | Journal Article |
| id | ntu-10356/175653 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2025-03-09T11:58:43Z |
| publishDate | 2024 |
| record_format | dspace |
| spelling | ntu-10356/1756532024-10-04T07:06:42Z Monotonic asynchronous two-bit full adder Balasubramanian, Padmanabhan Maskell, Douglas Leslie School of Computer Science and Engineering Hardware & Embedded Systems Lab (HESL) Computer and Information Science Engineering Asynchronous circuits Arithmetic circuits Logic design Digital circuits High-speed Low power design VLSI design Monotonic circuits are a class of input–output mode (IOM) asynchronous circuits that are relaxed compared to quasi-delay-insensitive (QDI) IOM asynchronous circuits in terms of signaling the completion of internal processing. Some recent works have demonstrated the superiority of monotonic logic over QDI logic for arithmetic circuits such as adders and multipliers. This paper presents a new monotonic asynchronous two-bit full adder (TFA) that can be duplicated and cascaded to form a ripple-carry adder (RCA). While an RCA is a slow adder with respect to synchronous design, with respect to IOM asynchronous design an RCA is a noteworthy adder since it has perhaps the least reverse latency that is not attainable through other IOM asynchronous adders. Conventionally, an RCA is constructed via a cascade of one-bit full adders (OFAs). An OFA adds two input bits along with any carry input and produces a sum bit and any carry output. On the other hand, a TFA simultaneously adds two pairs of input bits along with any carry input and produces two sum bits and any carry output. Using our proposed monotonic TFA, we realized an RCA to compare its performance with RCAs constructed using different asynchronous OFAs, and RCAs constructed using existing TFAs. We considered the popular delay-insensitive dual-rail scheme for encoding the adder inputs and outputs, and two 4-phase handshake protocols, namely return-to-zero handshaking (R0H) and return-to-one handshaking (R1H) for communication separately. We used a 28 nm CMOS process for implementation and considered a 32-bit addition as an example. Based on the design metrics estimated, the following inferences were derived: (i) compared to the RCA using the state-of-the-art monotonic OFA, the RCA incorporating the proposed TFA achieved a 26% reduction in cycle time for R0H and a 28.5% reduction in cycle time for R1H while dissipating almost the same power; the cycle time governs the data application rate in an IOM asynchronous circuit, and (ii) compared to the RCA comprising an early output QDI TFA, the RCA incorporating the proposed TFA achieved a 22.3% reduction in cycle time for R0H and a 25.4% reduction in cycle time for R1H while dissipating moderately less power. Also, compared to the existing early output QDI TFA, the proposed TFA occupies 40.9% less area for R0H and 42% less area for R1H. Ministry of Education (MOE) Published version This research was partially funded by the Singapore Ministry of Education (MOE), Academic Research Fund under grant number Tier-1 RG127/22. 2024-05-02T02:51:47Z 2024-05-02T02:51:47Z 2024 Journal Article Balasubramanian, P. & Maskell, D. L. (2024). Monotonic asynchronous two-bit full adder. Electronics, 13(9), 1717-. https://dx.doi.org/10.3390/electronics13091717 2079-9292 https://hdl.handle.net/10356/175653 10.3390/electronics13091717 9 13 1717 en RG127/22 Electronics © 2024 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/). application/pdf |
| spellingShingle | Computer and Information Science Engineering Asynchronous circuits Arithmetic circuits Logic design Digital circuits High-speed Low power design VLSI design Balasubramanian, Padmanabhan Maskell, Douglas Leslie Monotonic asynchronous two-bit full adder |
| title | Monotonic asynchronous two-bit full adder |
| title_full | Monotonic asynchronous two-bit full adder |
| title_fullStr | Monotonic asynchronous two-bit full adder |
| title_full_unstemmed | Monotonic asynchronous two-bit full adder |
| title_short | Monotonic asynchronous two-bit full adder |
| title_sort | monotonic asynchronous two bit full adder |
| topic | Computer and Information Science Engineering Asynchronous circuits Arithmetic circuits Logic design Digital circuits High-speed Low power design VLSI design |
| url | https://hdl.handle.net/10356/175653 |
| work_keys_str_mv | AT balasubramanianpadmanabhan monotonicasynchronoustwobitfulladder AT maskelldouglasleslie monotonicasynchronoustwobitfulladder |