| Summary: | The evolution of Internet of Things (IoT) has seen a progression from simple data collection to more sophisticated, self-organizing system formed of a large number of sensor nodes capable of data capture, transmission and processing. Throughout this evolution, SRAM has played a pivotal role in providing fast and reliable cache memory for buffering the data and facilitating real-time edge computation. As IoT applications increasingly rely on battery power, there is a growing demand for low-power SRAM. Voltage scaling SRAM into subthreshold region presents a promising solution for enhancing energy efficiency, as the subthreshold current exhibit an exponential relationship with the voltage. Hence, this project evaluated 6T, 8T and 10T bit cell topology on their stability, power, timing, and reliability performance under both super-threshold and subthreshold regions. Subsequently, after balancing the trade-offs among all the performance metrics, a 1024-bit SRAM array is implemented using 8T bit cell considering its smallest leakage power and decent static noise margin. The SRAM array built is capable of reading or writing 16 bit data, and operating reliably at a supply voltage down to 0.3V with leakage power of 17.3nW, read energy of 13.2fJ and write energy of 18.1fJ and maximum operating frequency of 1M Hz.
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