| Summary: | In recent years, there has been growing interest in multi-valued logic (MVL) circuits, especially ternary logic circuits, due to their higher information density compared to binary logic systems. However, challenges persist regarding the fundamental construction of MVL circuit standard cells and the issues of CMOS fabrication compatibility. In this project, various ternary arithmetic circuits including balanced and unbalanced half as well as full adders are designed.
This study delves into the design and optimization of ternary logic circuits, utilising diverse methodologies to enhance their performance metrics. Initially, ternary gates such as SUM, CARRY, (Not anything) NANY, and (Not consensus) NCONS are created using the Quine-McCluskey algorithm, synthesising the design of logic circuits for both balanced and unbalanced adders to evaluate essential performance parameters. Subsequently, a similar methodology is employed to develop both unbalanced and balanced 1-trit multipliers. Finally, high-speed ternary 4-trit by 4-trit Dadda tree multipliers are proposed and developed via a stage-by-stage reduction approach.
Comparative analysis reveals significant improvements in worst-case time delay and power-delay product (PDP) compared to conventional array multipliers. Notably, the ternary unbalanced Dadda tree multiplier demonstrates an average PDP enhancement of 41.5%, while the balanced counterpart exhibits a 42.66% reduction in PDP, both operating at a frequency of 4 MHz. These findings underscore the effectiveness of the proposed methodologies in advancing ternary logic circuit design towards heightened performance and efficiency.
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