| Summary: | This thesis explores the design of a 10-bit Segmented Current Steering Digital-to-Analog Converter (SCSDAC), focusing on optimizing performance under stringent power constraints. The DAC is meticulously crafted to minimize power usage and maximize efficiency, aiming to operate below the conventional power usage of 10 to 50 milliwatts, with a targeted consumption under 20 microwatts. By refining the DAC architecture to address inherent limitations such as glitches and linearity, the study achieves a significant reduction in power consumption without compromising on the quality and efficiency of data conversion, which is critical for modern communication technologies.
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