The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC)
This thesis explores the design of a 10-bit Segmented Current Steering Digital-to-Analog Converter (SCSDAC), focusing on optimizing performance under stringent power constraints. The DAC is meticulously crafted to minimize power usage and maximize efficiency, aiming to operate below the conventional...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
Nanyang Technological University
2024
|
| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/177198 |
| _version_ | 1811687408085762048 |
|---|---|
| author | Xu, Pengbo |
| author2 | Siek Liter |
| author_facet | Siek Liter Xu, Pengbo |
| author_sort | Xu, Pengbo |
| collection | NTU |
| description | This thesis explores the design of a 10-bit Segmented Current Steering Digital-to-Analog Converter (SCSDAC), focusing on optimizing performance under stringent power constraints. The DAC is meticulously crafted to minimize power usage and maximize efficiency, aiming to operate below the conventional power usage of 10 to 50 milliwatts, with a targeted consumption under 20 microwatts. By refining the DAC architecture to address inherent limitations such as glitches and linearity, the study achieves a significant reduction in power consumption without compromising on the quality and efficiency of data conversion, which is critical for modern communication technologies. |
| first_indexed | 2024-10-01T05:15:50Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/177198 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:15:50Z |
| publishDate | 2024 |
| publisher | Nanyang Technological University |
| record_format | dspace |
| spelling | ntu-10356/1771982024-05-31T15:43:50Z The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC) Xu, Pengbo Siek Liter School of Electrical and Electronic Engineering ELSIEK@ntu.edu.sg Engineering DAC Low power This thesis explores the design of a 10-bit Segmented Current Steering Digital-to-Analog Converter (SCSDAC), focusing on optimizing performance under stringent power constraints. The DAC is meticulously crafted to minimize power usage and maximize efficiency, aiming to operate below the conventional power usage of 10 to 50 milliwatts, with a targeted consumption under 20 microwatts. By refining the DAC architecture to address inherent limitations such as glitches and linearity, the study achieves a significant reduction in power consumption without compromising on the quality and efficiency of data conversion, which is critical for modern communication technologies. Bachelor's degree 2024-05-27T02:42:00Z 2024-05-27T02:42:00Z 2024 Final Year Project (FYP) Xu, P. (2024). The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC). Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/177198 https://hdl.handle.net/10356/177198 en application/pdf Nanyang Technological University |
| spellingShingle | Engineering DAC Low power Xu, Pengbo The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC) |
| title | The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC) |
| title_full | The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC) |
| title_fullStr | The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC) |
| title_full_unstemmed | The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC) |
| title_short | The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC) |
| title_sort | design of a 10 bit segmented current steering digital to analog converter scsdac |
| topic | Engineering DAC Low power |
| url | https://hdl.handle.net/10356/177198 |
| work_keys_str_mv | AT xupengbo thedesignofa10bitsegmentedcurrentsteeringdigitaltoanalogconverterscsdac AT xupengbo designofa10bitsegmentedcurrentsteeringdigitaltoanalogconverterscsdac |