| Summary: | Fast Fourier transform (FFT) plays an important part as a signal processing function in many applications. This report will represent a single-path pipelined hardware structure and its implementation on field programmable gates-array (FPGA) for discrete Fourier transform (DFT) computation based on the radix-22 FFT algorithm. The proposed structure requires log4N-1 complex multipliers, log2N complex adder/subtractors and 2(N-1) complex data stores. Compared with the previous radix-22 SDF structure, the number of adder/subtractors is reduced by 50%. Compared with the previous radix-22 MDC structure, the number of both complex multipliers and adder/subtractors is reduced by 50%. The report will give the detailed description of the implementation of the structure on FPGA. At the same time, the in depth comparison between the proposed structure and radix-22 SDF structures will be presented.
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