Implementation of fast algorithms of discrete fourier transform with FPGA
Fast Fourier transform (FFT) plays an important part as a signal processing function in many applications. This report will represent a single-path pipelined hardware structure and its implementation on field programmable gates-array (FPGA) for discrete Fourier transform (DFT) computation based on t...
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Format: | Final Year Project (FYP) |
Language: | English |
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2009
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Online Access: | http://hdl.handle.net/10356/17847 |
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author | Zhang, Yanghao. |
author2 | Bi Guoan |
author_facet | Bi Guoan Zhang, Yanghao. |
author_sort | Zhang, Yanghao. |
collection | NTU |
description | Fast Fourier transform (FFT) plays an important part as a signal processing function in many applications. This report will represent a single-path pipelined hardware structure and its implementation on field programmable gates-array (FPGA) for discrete Fourier transform (DFT) computation based on the radix-22 FFT algorithm. The proposed structure requires log4N-1 complex multipliers, log2N complex adder/subtractors and 2(N-1) complex data stores. Compared with the previous radix-22 SDF structure, the number of adder/subtractors is reduced by 50%. Compared with the previous radix-22 MDC structure, the number of both complex multipliers and adder/subtractors is reduced by 50%. The report will give the detailed description of the implementation of the structure on FPGA. At the same time, the in depth comparison between the proposed structure and radix-22 SDF structures will be presented. |
first_indexed | 2024-10-01T05:12:39Z |
format | Final Year Project (FYP) |
id | ntu-10356/17847 |
institution | Nanyang Technological University |
language | English |
last_indexed | 2024-10-01T05:12:39Z |
publishDate | 2009 |
record_format | dspace |
spelling | ntu-10356/178472019-12-10T14:47:39Z Implementation of fast algorithms of discrete fourier transform with FPGA Zhang, Yanghao. Bi Guoan School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing Fast Fourier transform (FFT) plays an important part as a signal processing function in many applications. This report will represent a single-path pipelined hardware structure and its implementation on field programmable gates-array (FPGA) for discrete Fourier transform (DFT) computation based on the radix-22 FFT algorithm. The proposed structure requires log4N-1 complex multipliers, log2N complex adder/subtractors and 2(N-1) complex data stores. Compared with the previous radix-22 SDF structure, the number of adder/subtractors is reduced by 50%. Compared with the previous radix-22 MDC structure, the number of both complex multipliers and adder/subtractors is reduced by 50%. The report will give the detailed description of the implementation of the structure on FPGA. At the same time, the in depth comparison between the proposed structure and radix-22 SDF structures will be presented. Bachelor of Engineering 2009-06-17T03:26:40Z 2009-06-17T03:26:40Z 2009 2009 Final Year Project (FYP) http://hdl.handle.net/10356/17847 en Nanyang Technological University 63 p. application/msword |
spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing Zhang, Yanghao. Implementation of fast algorithms of discrete fourier transform with FPGA |
title | Implementation of fast algorithms of discrete fourier transform with FPGA |
title_full | Implementation of fast algorithms of discrete fourier transform with FPGA |
title_fullStr | Implementation of fast algorithms of discrete fourier transform with FPGA |
title_full_unstemmed | Implementation of fast algorithms of discrete fourier transform with FPGA |
title_short | Implementation of fast algorithms of discrete fourier transform with FPGA |
title_sort | implementation of fast algorithms of discrete fourier transform with fpga |
topic | DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing |
url | http://hdl.handle.net/10356/17847 |
work_keys_str_mv | AT zhangyanghao implementationoffastalgorithmsofdiscretefouriertransformwithfpga |