| Summary: | Integrated circuits (ICs) are imperative in modern satellites, particularly as the space industry evolves from ‘Traditional Space’ to ‘New Space’. In particular, ICs need to feature reliability whilst operating in an irradiation environment, i.e., they would need to be radiation-hardened or -tolerant to single-event-effects and to total ionization dosage. For digital circuits, the specific single-event-effects of concern are Single-Event-Transients (SETs) and Single-Event-Upsets (SEUs). When an SET occurs, it introduces a transient fault current pulse into the circuit, momentarily disrupting normal operations and potentially leading to an SEU.
This dissertation aims to mitigate SETs by means of the design of digital cells in a digital cell library based on the Radiation-Hardened by Design (RHBD) methodology. The radiation hardness in our design involves increasing the transistor gate width, which enhances the drain currents and thereby mitigates the impact of fault transient current pulses caused by SETs. SET simulations are performed to determine the optimal gate width required to withstand specific intensities (Linear Energy Transfer levels) of radiation. Subsequently, using the parameters and design rules of the Global Foundries 130nm BCDLite process, eight library cells including D-latches, D-flip-flops (DFFs), and scan-chain DFFs are designed and validated through both pre-layout and post-layout simulations.
This dissertation also implements a custom Advanced Encryption Standard (AES) algorithm module in Verilog. Both pre-synthesis and post-synthesis simulations are performed, demonstrating that the design meets all specified requirements. This implementation not only exemplifies the typical front-end design flow but also suggests that other modules can be successfully designed and implemented using some the RHBD library cells developed in this dissertation.
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