Energy efficient software-hardware co-design of quantized recurrent convolutional neural network for continuous cardiac monitoring
This paper presents an electrocardiogram (ECG) signal classification model based on Recurrent Convolutional Neural Network (RCNN). With recurrent connections and data buffers, a single convolutional layer is reused to implement multiple layers function. Using a 5-layers CNN network as an example, th...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
| Published: |
2024
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| Online Access: | https://hdl.handle.net/10356/179110 https://ieeexplore.ieee.org/abstract/document/10168601 |
| _version_ | 1811682971701215232 |
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| author | Hu, Jinhai Leow, Cong Sheng Goh, Wang Ling Gao, Yuan |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Hu, Jinhai Leow, Cong Sheng Goh, Wang Ling Gao, Yuan |
| author_sort | Hu, Jinhai |
| collection | NTU |
| description | This paper presents an electrocardiogram (ECG) signal classification model based on Recurrent Convolutional Neural Network (RCNN). With recurrent connections and data buffers, a single convolutional layer is reused to implement multiple layers function. Using a 5-layers CNN network as an example, this approach reduces the number of parameters by more than 50% while achieving the same feature extraction size. Furthermore, quantized RCNN (QRCNN) is proposed where the input signal, interlayer output, and kernel weights are quantized to unsigned INT8, INT4, and signed INT4 respectively. For hardware implementation, pipelining and data reuse within the 1-D convolution kernel can potentially reduce latency. QRCNN model achieved 98.08% validation accuracy on MIT-BIH datasets with only 1% degradation due to quantization. The estimated dynamic power consumption of the QRCNN is less than 60% of a conventional quantized CNN when implemented on a Xilinx Artix-7 FPGA, showing the potential for resource-constraint edge devices. |
| first_indexed | 2024-10-01T04:05:19Z |
| format | Conference Paper |
| id | ntu-10356/179110 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:05:19Z |
| publishDate | 2024 |
| record_format | dspace |
| spelling | ntu-10356/1791102024-07-19T15:39:05Z Energy efficient software-hardware co-design of quantized recurrent convolutional neural network for continuous cardiac monitoring Hu, Jinhai Leow, Cong Sheng Goh, Wang Ling Gao, Yuan School of Electrical and Electronic Engineering 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS) Institute of Microelectronics, A*STAR Centre for Integrated Circuits and Systems Engineering ECG classification RCNN Fixed-point quantization FPGA This paper presents an electrocardiogram (ECG) signal classification model based on Recurrent Convolutional Neural Network (RCNN). With recurrent connections and data buffers, a single convolutional layer is reused to implement multiple layers function. Using a 5-layers CNN network as an example, this approach reduces the number of parameters by more than 50% while achieving the same feature extraction size. Furthermore, quantized RCNN (QRCNN) is proposed where the input signal, interlayer output, and kernel weights are quantized to unsigned INT8, INT4, and signed INT4 respectively. For hardware implementation, pipelining and data reuse within the 1-D convolution kernel can potentially reduce latency. QRCNN model achieved 98.08% validation accuracy on MIT-BIH datasets with only 1% degradation due to quantization. The estimated dynamic power consumption of the QRCNN is less than 60% of a conventional quantized CNN when implemented on a Xilinx Artix-7 FPGA, showing the potential for resource-constraint edge devices. Agency for Science, Technology and Research (A*STAR) Submitted/Accepted version This work was supported by the Agency for Science, Technology and Research (A*STAR), Singapore under the Cyber-Physiochemical Interface programme, grant No. A18A1b0045. 2024-07-19T05:23:31Z 2024-07-19T05:23:31Z 2023 Conference Paper Hu, J., Leow, C. S., Goh, W. L. & Gao, Y. (2023). Energy efficient software-hardware co-design of quantized recurrent convolutional neural network for continuous cardiac monitoring. 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS). https://dx.doi.org/10.1109/AICAS57966.2023.10168601 979-8-3503-3267-4 https://hdl.handle.net/10356/179110 10.1109/AICAS57966.2023.10168601 https://ieeexplore.ieee.org/abstract/document/10168601 en A18A1b0045 © 2023 IEEE. All rights reserved. This article may be downloaded for personal use only. Any other use requires prior permission of the copyright holder. The Version of Record is available online at http://doi.org/10.1109/AICAS57966.2023.10168601. application/pdf |
| spellingShingle | Engineering ECG classification RCNN Fixed-point quantization FPGA Hu, Jinhai Leow, Cong Sheng Goh, Wang Ling Gao, Yuan Energy efficient software-hardware co-design of quantized recurrent convolutional neural network for continuous cardiac monitoring |
| title | Energy efficient software-hardware co-design of quantized recurrent convolutional neural network for continuous cardiac monitoring |
| title_full | Energy efficient software-hardware co-design of quantized recurrent convolutional neural network for continuous cardiac monitoring |
| title_fullStr | Energy efficient software-hardware co-design of quantized recurrent convolutional neural network for continuous cardiac monitoring |
| title_full_unstemmed | Energy efficient software-hardware co-design of quantized recurrent convolutional neural network for continuous cardiac monitoring |
| title_short | Energy efficient software-hardware co-design of quantized recurrent convolutional neural network for continuous cardiac monitoring |
| title_sort | energy efficient software hardware co design of quantized recurrent convolutional neural network for continuous cardiac monitoring |
| topic | Engineering ECG classification RCNN Fixed-point quantization FPGA |
| url | https://hdl.handle.net/10356/179110 https://ieeexplore.ieee.org/abstract/document/10168601 |
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