RISC-V processor FPGA implementation
RISC-V is an open-standard Instruction Set Architecture (ISA), and RV32I is a subset of RISC-V instructions. The simplicity of RV32I makes it ideal for educational purposes. This project is to implement a RISC-V (RV32I) Processor (softcore with a simple Harvard architecture) on Nexys A7 Xilinx A...
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| Format: | Final Year Project (FYP) |
| Language: | English |
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Nanyang Technological University
2024
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| Online Access: | https://hdl.handle.net/10356/181173 |