Simulation and verification of IP cores for PCI and ethernet application
PCI and Ethernet MAC are two most essential and widely-used modules in computer systems and networking. A project was carried to study two IP Cores, namely a PCI Bridge IP Core and an Ethernet MAC IP Core, aiming to understand the functionalities and specifications of the two cores, hence facilit...
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| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2009
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| Online Access: | http://hdl.handle.net/10356/18187 |
| _version_ | 1811679912533164032 |
|---|---|
| author | Xu, Ying. |
| author2 | Jong Ching Chuen |
| author_facet | Jong Ching Chuen Xu, Ying. |
| author_sort | Xu, Ying. |
| collection | NTU |
| description | PCI and Ethernet MAC are two most essential and widely-used modules in computer
systems and networking. A project was carried to study two IP Cores, namely a PCI
Bridge IP Core and an Ethernet MAC IP Core, aiming to understand the
functionalities and specifications of the two cores, hence facilitating the reuse of
these cores in ASICs (Application Specific Integrated Circuits). The report covers the
study, simulation and verification of the two cores.
The two IP cores are available as synthesizable RTL (Register Transfer Level) core
coded in Verilog HDL (Hardware Description Language). The codes and
functionalities of the two cores were first studied and analyzed. Their functionalities
were compared with the PCI and the Ethernet MAC standard specification. To verify
their functionalities, a set of testbenches was developed in Verilog HDL, targeting the
main functions of the cores, namely data transactions, configuration and interrupt
reaction. An integrated system consisting of the two cores was then created to form a
complete communication link and a system level testbench was developed to verify
the integrated system.
The report presents the details of the functionality and specification description of
the two cores, the testbenches developed, the simulation process and the results
obtained as well as the result analysis. Some problems encountered and the solutions
found are discussed. Some suggestions for future work are also included in the
report. |
| first_indexed | 2024-10-01T03:16:42Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/18187 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T03:16:42Z |
| publishDate | 2009 |
| record_format | dspace |
| spelling | ntu-10356/181872023-07-07T15:43:41Z Simulation and verification of IP cores for PCI and ethernet application Xu, Ying. Jong Ching Chuen School of Electrical and Electronic Engineering Centre for Integrated Circuits and Systems DRNTU::Engineering::Electrical and electronic engineering::Wireless communication systems PCI and Ethernet MAC are two most essential and widely-used modules in computer systems and networking. A project was carried to study two IP Cores, namely a PCI Bridge IP Core and an Ethernet MAC IP Core, aiming to understand the functionalities and specifications of the two cores, hence facilitating the reuse of these cores in ASICs (Application Specific Integrated Circuits). The report covers the study, simulation and verification of the two cores. The two IP cores are available as synthesizable RTL (Register Transfer Level) core coded in Verilog HDL (Hardware Description Language). The codes and functionalities of the two cores were first studied and analyzed. Their functionalities were compared with the PCI and the Ethernet MAC standard specification. To verify their functionalities, a set of testbenches was developed in Verilog HDL, targeting the main functions of the cores, namely data transactions, configuration and interrupt reaction. An integrated system consisting of the two cores was then created to form a complete communication link and a system level testbench was developed to verify the integrated system. The report presents the details of the functionality and specification description of the two cores, the testbenches developed, the simulation process and the results obtained as well as the result analysis. Some problems encountered and the solutions found are discussed. Some suggestions for future work are also included in the report. Bachelor of Engineering 2009-06-24T01:12:54Z 2009-06-24T01:12:54Z 2009 2009 Final Year Project (FYP) http://hdl.handle.net/10356/18187 en Nanyang Technological University 96 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Wireless communication systems Xu, Ying. Simulation and verification of IP cores for PCI and ethernet application |
| title | Simulation and verification of IP cores for PCI and ethernet application |
| title_full | Simulation and verification of IP cores for PCI and ethernet application |
| title_fullStr | Simulation and verification of IP cores for PCI and ethernet application |
| title_full_unstemmed | Simulation and verification of IP cores for PCI and ethernet application |
| title_short | Simulation and verification of IP cores for PCI and ethernet application |
| title_sort | simulation and verification of ip cores for pci and ethernet application |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Wireless communication systems |
| url | http://hdl.handle.net/10356/18187 |
| work_keys_str_mv | AT xuying simulationandverificationofipcoresforpciandethernetapplication |