Design and optimization of high-density ternary logic memory circuits
With the continuous advancement of information technology, storage technologies are facing challenges in capacity, energy efficiency, and reliability. Traditional binary storage technologies are nearing their physical limits, while multi-valued technology, particularly ternary technology, offers the...
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| Format: | Thesis-Master by Coursework |
| Language: | English |
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Nanyang Technological University
2025
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| Online Access: | https://hdl.handle.net/10356/182793 |
| _version_ | 1826111342885470208 |
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| author | Yang, Zepeng |
| author2 | Tay Beng Kang |
| author_facet | Tay Beng Kang Yang, Zepeng |
| author_sort | Yang, Zepeng |
| collection | NTU |
| description | With the continuous advancement of information technology, storage technologies are facing challenges in capacity, energy efficiency, and reliability. Traditional binary storage technologies are nearing their physical limits, while multi-valued technology, particularly ternary technology, offers the potential for higher storage density and lower power consumption. This is because ternary technology can store more logic states within the same storage unit and reduce interconnect resource consumption. The application of ternary storage technology, particularly in Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), has become a key factor in improving the performance of next-generation storage systems. This dissertation explores the circuit design and optimization of ternary DRAM and SRAM cells, addressing the limitations of traditional binary storage technologies in terms of density, energy efficiency and reliability. Utilizing the SMIC180 process design kit, the study employs Cadence Virtuoso and Spectre tools for design and simulation. Two innovative ternary DRAM structures, including 2-Transistor Gain-Cell Embedded DRAM (2T GC-eDRAM) and 4-Transistor Gain-Cell Embedded DRAM (4T GC-eDRAM), and two ternary SRAM structures, including differential bit line structure and single-ended bit line structure, are proposed. The 2T GC-eDRAM offers simplicity and compactness but exhibits a shorter data retention time due to leakage currents in the write path. In contrast, the 4T GC-eDRAM significantly extends data retention by approximately 8–15 times through a feedback mechanism, albeit at the cost of increased area and write delay. In SRAM design, differential bit line structure improves the accuracy and speed of data operation by separating the read and write paths, while single-ended bit line structure is more advantageous in simplifying the layout and reducing the area. In addition, the study evaluates the impact of the Standard Ternary Inverter (STI) on SRAM performance. Verified by simulation, the ternary storage cells proposed in this research shows excellent performance in storing and write/read multi-valued logic states. This research provides crucial theoretical and practical support for high-density storage systems and embedded applications. These results lay the foundation for the further development of multi-valued storage technology and demonstrate its broad application prospects in next-generation high-performance storage systems. |
| first_indexed | 2025-03-09T10:18:06Z |
| format | Thesis-Master by Coursework |
| id | ntu-10356/182793 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2025-03-09T10:18:06Z |
| publishDate | 2025 |
| publisher | Nanyang Technological University |
| record_format | dspace |
| spelling | ntu-10356/1827932025-02-28T15:48:48Z Design and optimization of high-density ternary logic memory circuits Yang, Zepeng Tay Beng Kang School of Electrical and Electronic Engineering CNRS International NTU THALES Research Alliances EBKTAY@ntu.edu.sg Engineering Ternary logic DRAM SRAM With the continuous advancement of information technology, storage technologies are facing challenges in capacity, energy efficiency, and reliability. Traditional binary storage technologies are nearing their physical limits, while multi-valued technology, particularly ternary technology, offers the potential for higher storage density and lower power consumption. This is because ternary technology can store more logic states within the same storage unit and reduce interconnect resource consumption. The application of ternary storage technology, particularly in Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), has become a key factor in improving the performance of next-generation storage systems. This dissertation explores the circuit design and optimization of ternary DRAM and SRAM cells, addressing the limitations of traditional binary storage technologies in terms of density, energy efficiency and reliability. Utilizing the SMIC180 process design kit, the study employs Cadence Virtuoso and Spectre tools for design and simulation. Two innovative ternary DRAM structures, including 2-Transistor Gain-Cell Embedded DRAM (2T GC-eDRAM) and 4-Transistor Gain-Cell Embedded DRAM (4T GC-eDRAM), and two ternary SRAM structures, including differential bit line structure and single-ended bit line structure, are proposed. The 2T GC-eDRAM offers simplicity and compactness but exhibits a shorter data retention time due to leakage currents in the write path. In contrast, the 4T GC-eDRAM significantly extends data retention by approximately 8–15 times through a feedback mechanism, albeit at the cost of increased area and write delay. In SRAM design, differential bit line structure improves the accuracy and speed of data operation by separating the read and write paths, while single-ended bit line structure is more advantageous in simplifying the layout and reducing the area. In addition, the study evaluates the impact of the Standard Ternary Inverter (STI) on SRAM performance. Verified by simulation, the ternary storage cells proposed in this research shows excellent performance in storing and write/read multi-valued logic states. This research provides crucial theoretical and practical support for high-density storage systems and embedded applications. These results lay the foundation for the further development of multi-valued storage technology and demonstrate its broad application prospects in next-generation high-performance storage systems. Master's degree 2025-02-26T07:19:34Z 2025-02-26T07:19:34Z 2025 Thesis-Master by Coursework Yang, Z. (2025). Design and optimization of high-density ternary logic memory circuits. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/182793 https://hdl.handle.net/10356/182793 en application/pdf Nanyang Technological University |
| spellingShingle | Engineering Ternary logic DRAM SRAM Yang, Zepeng Design and optimization of high-density ternary logic memory circuits |
| title | Design and optimization of high-density ternary logic memory circuits |
| title_full | Design and optimization of high-density ternary logic memory circuits |
| title_fullStr | Design and optimization of high-density ternary logic memory circuits |
| title_full_unstemmed | Design and optimization of high-density ternary logic memory circuits |
| title_short | Design and optimization of high-density ternary logic memory circuits |
| title_sort | design and optimization of high density ternary logic memory circuits |
| topic | Engineering Ternary logic DRAM SRAM |
| url | https://hdl.handle.net/10356/182793 |
| work_keys_str_mv | AT yangzepeng designandoptimizationofhighdensityternarylogicmemorycircuits |