Class D amplifier based on random modulation technique
This dissertation presents the design of a Class-D Amplifier with a randomly modulated clock to minimize electromagnetic interference. The clock frequency varies between 110 kHz and 3(X) kHz and the depth of variation is proportional to the input signal to maintain a good SNR when input signal is lo...
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| Format: | Thesis |
| Language: | English |
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2009
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| Online Access: | http://hdl.handle.net/10356/18790 |
| _version_ | 1826118746695008256 |
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| author | Erbito Rogelio Jr Lucero |
| author2 | Tan Meng Tong |
| author_facet | Tan Meng Tong Erbito Rogelio Jr Lucero |
| author_sort | Erbito Rogelio Jr Lucero |
| collection | NTU |
| description | This dissertation presents the design of a Class-D Amplifier with a randomly modulated clock to minimize electromagnetic interference. The clock frequency varies between 110 kHz and 3(X) kHz and the depth of variation is proportional to the input signal to maintain a good SNR when input signal is low. Besides random clock modulation, frequency modulation has also been introduced to improve the efficiency. The proposed technique will minimize the common-mode interference in the two speaker’s wires of a filterless Class D amplifier so that the switching amplifier can pass the international standards such as the FCC Class B limits. The proposed design also exhibits better efficiency at low input signal. The circuit can operate between a supply voltage of 2.5V and 4V using the 0.35um CMOS process. |
| first_indexed | 2024-10-01T04:48:31Z |
| format | Thesis |
| id | ntu-10356/18790 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:48:31Z |
| publishDate | 2009 |
| record_format | dspace |
| spelling | ntu-10356/187902023-07-04T15:25:10Z Class D amplifier based on random modulation technique Erbito Rogelio Jr Lucero Tan Meng Tong School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits This dissertation presents the design of a Class-D Amplifier with a randomly modulated clock to minimize electromagnetic interference. The clock frequency varies between 110 kHz and 3(X) kHz and the depth of variation is proportional to the input signal to maintain a good SNR when input signal is low. Besides random clock modulation, frequency modulation has also been introduced to improve the efficiency. The proposed technique will minimize the common-mode interference in the two speaker’s wires of a filterless Class D amplifier so that the switching amplifier can pass the international standards such as the FCC Class B limits. The proposed design also exhibits better efficiency at low input signal. The circuit can operate between a supply voltage of 2.5V and 4V using the 0.35um CMOS process. Master of Science (Integrated Circuit Design) 2009-07-20T01:16:17Z 2009-07-20T01:16:17Z 2008 2008 Thesis http://hdl.handle.net/10356/18790 en 96 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Erbito Rogelio Jr Lucero Class D amplifier based on random modulation technique |
| title | Class D amplifier based on random modulation technique |
| title_full | Class D amplifier based on random modulation technique |
| title_fullStr | Class D amplifier based on random modulation technique |
| title_full_unstemmed | Class D amplifier based on random modulation technique |
| title_short | Class D amplifier based on random modulation technique |
| title_sort | class d amplifier based on random modulation technique |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits |
| url | http://hdl.handle.net/10356/18790 |
| work_keys_str_mv | AT erbitorogeliojrlucero classdamplifierbasedonrandommodulationtechnique |