Testing of memory devices : a case study
The project examines the testing of the EPROM devices (on wafer) carried out in a local multinational company, analyses the fault coverage and proposes methods to improve the test yield. Using actual test yield data obtained from the test floor, the project examines and proposes to remove the need f...
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| Other Authors: | |
| Format: | Thesis |
| Language: | English |
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2009
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| Online Access: | http://hdl.handle.net/10356/19611 |
| _version_ | 1826124082042634240 |
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| author | Fong, Siew Cheong. |
| author2 | Ho, Duan Juat |
| author_facet | Ho, Duan Juat Fong, Siew Cheong. |
| author_sort | Fong, Siew Cheong. |
| collection | NTU |
| description | The project examines the testing of the EPROM devices (on wafer) carried out in a local multinational company, analyses the fault coverage and proposes methods to improve the test yield. Using actual test yield data obtained from the test floor, the project examines and proposes to remove the need for certain test processes like the thermal storage of EPROM which typically takes up between 12 to 48 hours. In addition, the industrial practice of testing of DRAM chips and its fault coverage are examined. It had been reported that with the use of lDDQ tests together with March Tests, the effectiveness for testing DRAM can be improved from an algorithm complexity of (16n) to (5n + 4), where n represents the number of cells in a DRAM. |
| first_indexed | 2024-10-01T06:14:50Z |
| format | Thesis |
| id | ntu-10356/19611 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:14:50Z |
| publishDate | 2009 |
| record_format | dspace |
| spelling | ntu-10356/196112023-07-04T15:49:01Z Testing of memory devices : a case study Fong, Siew Cheong. Ho, Duan Juat School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic systems The project examines the testing of the EPROM devices (on wafer) carried out in a local multinational company, analyses the fault coverage and proposes methods to improve the test yield. Using actual test yield data obtained from the test floor, the project examines and proposes to remove the need for certain test processes like the thermal storage of EPROM which typically takes up between 12 to 48 hours. In addition, the industrial practice of testing of DRAM chips and its fault coverage are examined. It had been reported that with the use of lDDQ tests together with March Tests, the effectiveness for testing DRAM can be improved from an algorithm complexity of (16n) to (5n + 4), where n represents the number of cells in a DRAM. Master of Science (Consumer Electronics) 2009-12-14T06:17:59Z 2009-12-14T06:17:59Z 1996 1996 Thesis http://hdl.handle.net/10356/19611 en NANYANG TECHNOLOGICAL UNIVERSITY 65 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Electronic systems Fong, Siew Cheong. Testing of memory devices : a case study |
| title | Testing of memory devices : a case study |
| title_full | Testing of memory devices : a case study |
| title_fullStr | Testing of memory devices : a case study |
| title_full_unstemmed | Testing of memory devices : a case study |
| title_short | Testing of memory devices : a case study |
| title_sort | testing of memory devices a case study |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Electronic systems |
| url | http://hdl.handle.net/10356/19611 |
| work_keys_str_mv | AT fongsiewcheong testingofmemorydevicesacasestudy |