Design and optimization of a low-voltage CMOS circuit for portable applications
In this project, a literature study on the existing low-voltage low-power CMOS static logic circuits is first performed. This report proposes a modified square root carry-select adder with high speed, small area and minimized power dissipation at a low operating voltage of 1.5V. This is achieved by...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis |
| Published: |
2008
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/3116 |
| Summary: | In this project, a literature study on the existing low-voltage low-power CMOS static logic circuits is first performed. This report proposes a modified square root carry-select adder with high speed, small area and minimized power dissipation at a low operating voltage of 1.5V. This is achieved by replacing the dual ripple-carry adders with a carry skip adder for zero-carry in. |
|---|