VHDL synthesis of Montgomery modular multiplier
This work describes the characteristics of two architectures designed to implement modular multiplication using the Montgomery Modular algorithm: the first FPGA design has an iterative sequential architecture while the second has a systolic array-based architecture. The first architecture proposed i...
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| Format: | Thesis |
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2008
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| Online Access: | http://hdl.handle.net/10356/3197 |