Integrated platform for design and verification of digital FIR filters
This work aimed at creating a unified platform to automate the generation of VHDL codes for the physical synthesis of FIR filters in both direct and transposed direct form filters. The aim was to provide designers and researchers with a tool to analyze the physical performances of different filter s...
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| Format: | Thesis |
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2008
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| Online Access: | https://hdl.handle.net/10356/3520 |
| _version_ | 1826111363822387200 |
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| author | Sharma Udit |
| author2 | Jong Ching Chuen |
| author_facet | Jong Ching Chuen Sharma Udit |
| author_sort | Sharma Udit |
| collection | NTU |
| description | This work aimed at creating a unified platform to automate the generation of VHDL codes for the physical synthesis of FIR filters in both direct and transposed direct form filters. The aim was to provide designers and researchers with a tool to analyze the physical performances of different filter solutions in terms of VLSI area, delay and power consumption. Many benchmark filters were collected for such evaluation. This platform also performs a functional verification of the VHDL codes by running parallel simulations in a simulator and comparing the final output with its
own response to randomly generated stimuli, thereby avoiding manual supervision. |
| first_indexed | 2024-10-01T02:49:29Z |
| format | Thesis |
| id | ntu-10356/3520 |
| institution | Nanyang Technological University |
| last_indexed | 2024-10-01T02:49:29Z |
| publishDate | 2008 |
| record_format | dspace |
| spelling | ntu-10356/35202023-07-04T16:56:46Z Integrated platform for design and verification of digital FIR filters Sharma Udit Jong Ching Chuen School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits This work aimed at creating a unified platform to automate the generation of VHDL codes for the physical synthesis of FIR filters in both direct and transposed direct form filters. The aim was to provide designers and researchers with a tool to analyze the physical performances of different filter solutions in terms of VLSI area, delay and power consumption. Many benchmark filters were collected for such evaluation. This platform also performs a functional verification of the VHDL codes by running parallel simulations in a simulator and comparing the final output with its own response to randomly generated stimuli, thereby avoiding manual supervision. MASTER OF ENGINEERING (EEE) 2008-09-17T09:31:32Z 2008-09-17T09:31:32Z 2007 2007 Thesis Sharma, U. (2007). Integrated platform for design and verification of digital FIR filters. Master’s thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/3520 10.32657/10356/3520 Nanyang Technological University application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Sharma Udit Integrated platform for design and verification of digital FIR filters |
| title | Integrated platform for design and verification of digital FIR filters |
| title_full | Integrated platform for design and verification of digital FIR filters |
| title_fullStr | Integrated platform for design and verification of digital FIR filters |
| title_full_unstemmed | Integrated platform for design and verification of digital FIR filters |
| title_short | Integrated platform for design and verification of digital FIR filters |
| title_sort | integrated platform for design and verification of digital fir filters |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits |
| url | https://hdl.handle.net/10356/3520 |
| work_keys_str_mv | AT sharmaudit integratedplatformfordesignandverificationofdigitalfirfilters |