Analysis and design of a digital class D power amplifier
Class D power amplifier has become more prevalent in consumer electronics due to its high power efficiency of more than 90%. Furthermore, in today’s increasing trend of digital processing, the use of a digital Class D power amplifier brings in additional benefits due to the elimination of the digita...
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| Format: | Final Year Project (FYP) |
| Language: | English |
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2010
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| Online Access: | http://hdl.handle.net/10356/40519 |
| _version_ | 1811692418742878208 |
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| author | Gan, Hoe Yee |
| author2 | Tan Meng Tong |
| author_facet | Tan Meng Tong Gan, Hoe Yee |
| author_sort | Gan, Hoe Yee |
| collection | NTU |
| description | Class D power amplifier has become more prevalent in consumer electronics due to its high power efficiency of more than 90%. Furthermore, in today’s increasing trend of digital processing, the use of a digital Class D power amplifier brings in additional benefits due to the elimination of the digital-to-analogue converter (DAC).
This report discussed in details, the effect of various building blocks of a digital Class D power amplifier on the total harmonics distortion (THD) and noise performance.
Two sampling process, namely the uniform sampling process and the delta compensation (δC) sampling process were discussed. MATLAB simulation results indicated that the THD of δC sampling process is significantly better than the uniform sampling process over the modulation range of 0.2 to 0.8.
In order to reduce the high clock rate required by the pulse generator in the digital Class D power amplifier, noise shaping techniques is employed. MATLAB simulation results indicated that when a 10-bits digital input stream for the pulse generator was noise shaped down to 5-bits, the clock frequency required by the pulse generator reduced by 32 times. Furthermore, this reduction in the clock frequency was couple with insignificant THD degradation.
For digital Class D power amplifier, the amount of power stage’s supply ripples translated to the analogue output could be reduced by employing a feedback system. MATLAB simulation results indicated that with a slight variation in its THD performance, a digital Class D power amplifier employing feedback system could achieve a significant power supply rejection ratio (PSRR) and power supply induced intermodulation distortion (PS-IMD) improvement of more than 55 dB and 18dB respectively, compare to one without feedback system.
A digital Class D power amplifier that gave the best compromise between THD, PSRR and PS-IMD improvement will be recommended. |
| first_indexed | 2024-10-01T06:35:28Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/40519 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:35:28Z |
| publishDate | 2010 |
| record_format | dspace |
| spelling | ntu-10356/405192023-07-07T17:26:21Z Analysis and design of a digital class D power amplifier Gan, Hoe Yee Tan Meng Tong School of Electrical and Electronic Engineering Centre for Integrated Circuits and Systems DRNTU::Engineering::Electrical and electronic engineering::Power electronics Class D power amplifier has become more prevalent in consumer electronics due to its high power efficiency of more than 90%. Furthermore, in today’s increasing trend of digital processing, the use of a digital Class D power amplifier brings in additional benefits due to the elimination of the digital-to-analogue converter (DAC). This report discussed in details, the effect of various building blocks of a digital Class D power amplifier on the total harmonics distortion (THD) and noise performance. Two sampling process, namely the uniform sampling process and the delta compensation (δC) sampling process were discussed. MATLAB simulation results indicated that the THD of δC sampling process is significantly better than the uniform sampling process over the modulation range of 0.2 to 0.8. In order to reduce the high clock rate required by the pulse generator in the digital Class D power amplifier, noise shaping techniques is employed. MATLAB simulation results indicated that when a 10-bits digital input stream for the pulse generator was noise shaped down to 5-bits, the clock frequency required by the pulse generator reduced by 32 times. Furthermore, this reduction in the clock frequency was couple with insignificant THD degradation. For digital Class D power amplifier, the amount of power stage’s supply ripples translated to the analogue output could be reduced by employing a feedback system. MATLAB simulation results indicated that with a slight variation in its THD performance, a digital Class D power amplifier employing feedback system could achieve a significant power supply rejection ratio (PSRR) and power supply induced intermodulation distortion (PS-IMD) improvement of more than 55 dB and 18dB respectively, compare to one without feedback system. A digital Class D power amplifier that gave the best compromise between THD, PSRR and PS-IMD improvement will be recommended. Bachelor of Engineering 2010-06-16T04:18:01Z 2010-06-16T04:18:01Z 2010 2010 Final Year Project (FYP) http://hdl.handle.net/10356/40519 en Nanyang Technological University 138 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Power electronics Gan, Hoe Yee Analysis and design of a digital class D power amplifier |
| title | Analysis and design of a digital class D power amplifier |
| title_full | Analysis and design of a digital class D power amplifier |
| title_fullStr | Analysis and design of a digital class D power amplifier |
| title_full_unstemmed | Analysis and design of a digital class D power amplifier |
| title_short | Analysis and design of a digital class D power amplifier |
| title_sort | analysis and design of a digital class d power amplifier |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Power electronics |
| url | http://hdl.handle.net/10356/40519 |
| work_keys_str_mv | AT ganhoeyee analysisanddesignofadigitalclassdpoweramplifier |