Design of the low-voltage CMOS sample-and-hold amplifier
A sample and hold circuit is used as a front-end sampler for the analog-to-digital converters. High-speed and low-power applications are more and more preferred. A fully differential CMOS sample and hold amplifier (SHA) is designed in this project. It is based on flip-around architecture. Double sam...
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| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
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2010
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| Online Access: | http://hdl.handle.net/10356/40686 |
| _version_ | 1826129530433044480 |
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| author | Li, Xiao Liang. |
| author2 | Siek Liter |
| author_facet | Siek Liter Li, Xiao Liang. |
| author_sort | Li, Xiao Liang. |
| collection | NTU |
| description | A sample and hold circuit is used as a front-end sampler for the analog-to-digital converters. High-speed and low-power applications are more and more preferred. A fully differential CMOS sample and hold amplifier (SHA) is designed in this project. It is based on flip-around architecture. Double sampling technique is used to achieve high speed without much extra power consumption. Bottom plate sampling and bootstrapping technique are also implemented to reduce clock feedthrough and improve linearity of the circuit. The operational transconductance amplifier (OTA) designed here uses folded cascode structure with both PMOS and NMOS input to increase input swing. Regulated cascode is used to increase the gain of the OTA. The SHA is implemented based on 0.18 μm CMOS technology. Using 1.8 V power supply and a signal swing of 0.6 Vpp, the SHA has achieved a resolution of 9 bits at a sampling rate of 400 MSample/s, with power consumption of 4.54 mW. |
| first_indexed | 2024-10-01T07:41:46Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/40686 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T07:41:46Z |
| publishDate | 2010 |
| record_format | dspace |
| spelling | ntu-10356/406862023-07-07T15:48:30Z Design of the low-voltage CMOS sample-and-hold amplifier Li, Xiao Liang. Siek Liter School of Electrical and Electronic Engineering DRNTU::Engineering A sample and hold circuit is used as a front-end sampler for the analog-to-digital converters. High-speed and low-power applications are more and more preferred. A fully differential CMOS sample and hold amplifier (SHA) is designed in this project. It is based on flip-around architecture. Double sampling technique is used to achieve high speed without much extra power consumption. Bottom plate sampling and bootstrapping technique are also implemented to reduce clock feedthrough and improve linearity of the circuit. The operational transconductance amplifier (OTA) designed here uses folded cascode structure with both PMOS and NMOS input to increase input swing. Regulated cascode is used to increase the gain of the OTA. The SHA is implemented based on 0.18 μm CMOS technology. Using 1.8 V power supply and a signal swing of 0.6 Vpp, the SHA has achieved a resolution of 9 bits at a sampling rate of 400 MSample/s, with power consumption of 4.54 mW. Bachelor of Engineering 2010-06-18T01:52:16Z 2010-06-18T01:52:16Z 2010 2010 Final Year Project (FYP) http://hdl.handle.net/10356/40686 en Nanyang Technological University 63 p. application/pdf |
| spellingShingle | DRNTU::Engineering Li, Xiao Liang. Design of the low-voltage CMOS sample-and-hold amplifier |
| title | Design of the low-voltage CMOS sample-and-hold amplifier |
| title_full | Design of the low-voltage CMOS sample-and-hold amplifier |
| title_fullStr | Design of the low-voltage CMOS sample-and-hold amplifier |
| title_full_unstemmed | Design of the low-voltage CMOS sample-and-hold amplifier |
| title_short | Design of the low-voltage CMOS sample-and-hold amplifier |
| title_sort | design of the low voltage cmos sample and hold amplifier |
| topic | DRNTU::Engineering |
| url | http://hdl.handle.net/10356/40686 |
| work_keys_str_mv | AT lixiaoliang designofthelowvoltagecmossampleandholdamplifier |