Modeling of PCI with SystemVerilog
Deep submicron semiconductor technology has enabled system-level IC design complexity to exceed millions of gates. This presents a major design and verification challenge that intensifies the demand for system-level design languages. A major impact in solving this problem has been the development...
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| Format: | Thesis |
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2008
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| Online Access: | http://hdl.handle.net/10356/4142 |
| _version_ | 1826125483772739584 |
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| author | Chithambaram Shaalini. |
| author2 | Jong, Ching Chuen |
| author_facet | Jong, Ching Chuen Chithambaram Shaalini. |
| author_sort | Chithambaram Shaalini. |
| collection | NTU |
| description | Deep submicron semiconductor technology has enabled system-level IC design
complexity to exceed millions of gates. This presents a major design and verification
challenge that intensifies the demand for system-level design languages. A major impact in solving this problem has been the development and standardization of an Hardware Description and Verification Language like SystemVerilog which caters all the needs for design as well as verification. |
| first_indexed | 2024-10-01T06:37:03Z |
| format | Thesis |
| id | ntu-10356/4142 |
| institution | Nanyang Technological University |
| last_indexed | 2024-10-01T06:37:03Z |
| publishDate | 2008 |
| record_format | dspace |
| spelling | ntu-10356/41422023-07-04T15:52:07Z Modeling of PCI with SystemVerilog Chithambaram Shaalini. Jong, Ching Chuen School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Deep submicron semiconductor technology has enabled system-level IC design complexity to exceed millions of gates. This presents a major design and verification challenge that intensifies the demand for system-level design languages. A major impact in solving this problem has been the development and standardization of an Hardware Description and Verification Language like SystemVerilog which caters all the needs for design as well as verification. Master of Science (Integrated Circuit Design) 2008-09-17T09:45:20Z 2008-09-17T09:45:20Z 2005 2005 Thesis http://hdl.handle.net/10356/4142 Nanyang Technological University application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Chithambaram Shaalini. Modeling of PCI with SystemVerilog |
| title | Modeling of PCI with SystemVerilog |
| title_full | Modeling of PCI with SystemVerilog |
| title_fullStr | Modeling of PCI with SystemVerilog |
| title_full_unstemmed | Modeling of PCI with SystemVerilog |
| title_short | Modeling of PCI with SystemVerilog |
| title_sort | modeling of pci with systemverilog |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
| url | http://hdl.handle.net/10356/4142 |
| work_keys_str_mv | AT chithambaramshaalini modelingofpciwithsystemverilog |