High performance architecture for move generation in computer chess : an FPGA based implementation

High performance architecture for move generation in computer chess : an FPGA based implementation

This thesis describes the design of a high performance parallel move generator architecture suitable for a high-speed chess computer. It illustrates how the complicated single task of chess move generation can be decomposed into several simple and independent atomic processors. These processors are...

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Bibliographic Details
Main Author: De Silva, C. R.
Other Authors: Amarasinghe, S. K.
Format: Thesis
Published: 2008
Subjects:
DRNTU::Engineering::Computer science and engineering::Computing methodologies::Artificial intelligence
DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
Online Access:http://hdl.handle.net/10356/4214

Internet

http://hdl.handle.net/10356/4214

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