| Summary: | Field programmable gate array (FPGA) processing units present considerably higher programming flexibility than other fixed architectures (e.g. microcontrollers (MCU’s), digital signal processors (DSP’s)). Although performances of FPGA are often compared to application-specific integrated circuits (ASIC’s), the price for such a flexibility of programmable devices is a significantly higher power consumption, compared to other fixed-architecture processors. Power consumption of FPGA implementations can be reduced at the low-level of design. However, for designs of moderate and high complexity such low-level approaches are tedious to implement and time-consuming. High (system) levels of design (e.g. algorithmic languages such as Handel-C) allow building systems of significantly higher complexity. Unfortunately, high-level design techniques have a limited (or no at all) ability to control power/energy properties of a design. The objective of our work is, therefore, to investigate the system-level approaches to power (and energy) efficiency of FPGA-based devices. FPGA’s dissipate static and dynamic power. However, only the dynamic power consumption is design-dependent, while static power consumption is mainly technology-dependent. Thus, we generally ignore the issues of static power reduction in the presented results. First, we show that power and energy properties of FPGA-based designs can be estimated with a reasonable precision at the high level of designing process. Moreover, we show that the system-level partitioning of designs into several clock domains (typically used to improve performance only) does not noticeably affect power consumption and hardware resources compared to the equivalent low-level partitioning. These two observations are the foundations of further experiments on system-level approaches to power and energy efficiency. We separately analyze the system-level parallel and sequential algorithm partitioning (in both cases employing the concept of multi-clock domains). It is shown that parallel algorithm partitioning can be optimized (by exploiting system-level estimates of domain sizes and timing) to provide substantial power consumption savings. Sequential partitioning was found a less efficient tool for reducing power and energy consumption of designs. However, we found that in sequentially partitioned designs power consumption losses can be minimized by selecting proper clock frequencies of a particular domain, if for certain reasons the domains must be run at diversified frequencies (which generally dramatically increases the overall energy usage). Finally, we analyze the total consumption of data-processing and data-transmission energies in FPGA-based designs (which is a typical problem for wireless sensor network (WSN) applications). In general, hardware requirements (i.e. power and energy) of data processing algorithms grow proportionally to the amount of data processed concurrently, while the energy required for transmission is proportional to the volume of transmitted data. We show that by combining system-level algorithms properties and characteristics of transmission modules, substantial savings of the overall energy are achievable. We believe that the proposed solutions will lead to more advanced system-level approaches to power and energy efficiency, i.e. development of tools incorporating low-level power and energy characteristics into high-level design methodologies. Such tools would have the ability to control low-level characteristics (e.g. power and energy consumption) of FPGA-based designs from the highest levels of abstraction.
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