Digital system design with FPGA using verilog HDL
In this final year project (Digital system design with FPGA using Verilog HDL) CORDIC is selected as the digital system to be designed. CORDIC is a simple and yet efficient algorithm for computing the hyperbolic and trigonometric functions, without the need of complex hardware multipliers and div...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2011
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/42749 |
| _version_ | 1826126303850397696 |
|---|---|
| author | Cho, Shao Ying. |
| author2 | Jong Ching Chuen |
| author_facet | Jong Ching Chuen Cho, Shao Ying. |
| author_sort | Cho, Shao Ying. |
| collection | NTU |
| description | In this final year project (Digital system design with FPGA using Verilog HDL)
CORDIC is selected as the digital system to be designed. CORDIC is a simple and yet
efficient algorithm for computing the hyperbolic and trigonometric functions, without the
need of complex hardware multipliers and dividers, thus reducing the speed of the
computation and the cost of the hardware tremendously. In the project, 2 versions of
CORDIC, namely a 16-bit and a 20-bit design, were designed and implemented. The
report details the design, implementation and hardware testing.
In this project, the CORDIC is designed to handle all the functions, including the cosine,
sine, tangent, hyperbolic cosine, hyperbolic sine, hyperbolic tangent, arctangent,
hyperbolic arctangent, vector, rotation, square root, exponential, division and nature
logarithm. The designs are coded in Verilog HDL. Their functionalities are simulated
with Xilinx ISE. After the functionalities are verified, the designs are synthesized and
implemented. They are also tested on a Xilinx Spartan 3E FPGA board. The detailed
designs of the modules are described and the design considerations are discussed.
Xilinx LogiCORETM IP CORDIC designs are also generated and compared with the
designs in this project. The comparison results in terms of result accuracy, hardware
resource utilization and computation speed are presented. |
| first_indexed | 2024-10-01T06:50:29Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/42749 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:50:29Z |
| publishDate | 2011 |
| record_format | dspace |
| spelling | ntu-10356/427492023-07-07T16:11:35Z Digital system design with FPGA using verilog HDL Cho, Shao Ying. Jong Ching Chuen School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic systems In this final year project (Digital system design with FPGA using Verilog HDL) CORDIC is selected as the digital system to be designed. CORDIC is a simple and yet efficient algorithm for computing the hyperbolic and trigonometric functions, without the need of complex hardware multipliers and dividers, thus reducing the speed of the computation and the cost of the hardware tremendously. In the project, 2 versions of CORDIC, namely a 16-bit and a 20-bit design, were designed and implemented. The report details the design, implementation and hardware testing. In this project, the CORDIC is designed to handle all the functions, including the cosine, sine, tangent, hyperbolic cosine, hyperbolic sine, hyperbolic tangent, arctangent, hyperbolic arctangent, vector, rotation, square root, exponential, division and nature logarithm. The designs are coded in Verilog HDL. Their functionalities are simulated with Xilinx ISE. After the functionalities are verified, the designs are synthesized and implemented. They are also tested on a Xilinx Spartan 3E FPGA board. The detailed designs of the modules are described and the design considerations are discussed. Xilinx LogiCORETM IP CORDIC designs are also generated and compared with the designs in this project. The comparison results in terms of result accuracy, hardware resource utilization and computation speed are presented. Bachelor of Engineering 2011-01-10T05:13:41Z 2011-01-10T05:13:41Z 2010 2010 Final Year Project (FYP) http://hdl.handle.net/10356/42749 en Nanyang Technological University 138 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Electronic systems Cho, Shao Ying. Digital system design with FPGA using verilog HDL |
| title | Digital system design with FPGA using verilog HDL |
| title_full | Digital system design with FPGA using verilog HDL |
| title_fullStr | Digital system design with FPGA using verilog HDL |
| title_full_unstemmed | Digital system design with FPGA using verilog HDL |
| title_short | Digital system design with FPGA using verilog HDL |
| title_sort | digital system design with fpga using verilog hdl |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Electronic systems |
| url | http://hdl.handle.net/10356/42749 |
| work_keys_str_mv | AT choshaoying digitalsystemdesignwithfpgausingveriloghdl |