VLSI implementation of a parser for MPEG-2 systems program stream
This report presents the VLSI design and implementation of a Parser for Program Stream of MPEG2 System Layer. The MPEG2 Program Stream Syntax, the Parser architecture, HDL implementation, simulation, synthesis and design timing analysis are discussed in detail.
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| Other Authors: | |
| Format: | Thesis |
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2008
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| Online Access: | http://hdl.handle.net/10356/4279 |
| _version_ | 1826122080754597888 |
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| author | Ashwin Pai Ballambettu. |
| author2 | Ho, Duan Juat |
| author_facet | Ho, Duan Juat Ashwin Pai Ballambettu. |
| author_sort | Ashwin Pai Ballambettu. |
| collection | NTU |
| description | This report presents the VLSI design and implementation of a Parser for Program Stream of MPEG2 System Layer. The MPEG2 Program Stream Syntax, the Parser architecture, HDL implementation, simulation, synthesis and design timing analysis are discussed in detail. |
| first_indexed | 2024-10-01T05:42:39Z |
| format | Thesis |
| id | ntu-10356/4279 |
| institution | Nanyang Technological University |
| last_indexed | 2024-10-01T05:42:39Z |
| publishDate | 2008 |
| record_format | dspace |
| spelling | ntu-10356/42792023-07-04T15:15:27Z VLSI implementation of a parser for MPEG-2 systems program stream Ashwin Pai Ballambettu. Ho, Duan Juat School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic systems DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems This report presents the VLSI design and implementation of a Parser for Program Stream of MPEG2 System Layer. The MPEG2 Program Stream Syntax, the Parser architecture, HDL implementation, simulation, synthesis and design timing analysis are discussed in detail. Master of Science (Consumer Electronics) 2008-09-17T09:48:13Z 2008-09-17T09:48:13Z 2005 2005 Thesis http://hdl.handle.net/10356/4279 Nanyang Technological University application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Electronic systems DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems Ashwin Pai Ballambettu. VLSI implementation of a parser for MPEG-2 systems program stream |
| title | VLSI implementation of a parser for MPEG-2 systems program stream |
| title_full | VLSI implementation of a parser for MPEG-2 systems program stream |
| title_fullStr | VLSI implementation of a parser for MPEG-2 systems program stream |
| title_full_unstemmed | VLSI implementation of a parser for MPEG-2 systems program stream |
| title_short | VLSI implementation of a parser for MPEG-2 systems program stream |
| title_sort | vlsi implementation of a parser for mpeg 2 systems program stream |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Electronic systems DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems |
| url | http://hdl.handle.net/10356/4279 |
| work_keys_str_mv | AT ashwinpaiballambettu vlsiimplementationofaparserformpeg2systemsprogramstream |