Design and implementation of formal verification methodology using Boolean satisfiability
Functional verification is an important phase in the design flow of digital circuits as it is used to verify a design when changes occur. It ensures that the functionality of the original design is not affected by the changes. Logic simulation is a widely used technique for the verification of a des...
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| Format: | Final Year Project (FYP) |
| Language: | English |
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2011
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| Online Access: | http://hdl.handle.net/10356/42896 |