Parallel assembly technique for thin chip using guided self-assembly
This report covers two parallel self-assembly techniques processes – Fluid Guided & Shape Fitting Guided self-assembly, with more emphasis placed on the latter. The principle of these techniques is based on nature‟s need for lowest energy state of all matter. The purpose of these techniques is...
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| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2011
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| Online Access: | http://hdl.handle.net/10356/44421 |
| _version_ | 1826118826065920000 |
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| author | Lee, Ming Kian. |
| author2 | Gan Chee Lip |
| author_facet | Gan Chee Lip Lee, Ming Kian. |
| author_sort | Lee, Ming Kian. |
| collection | NTU |
| description | This report covers two parallel self-assembly techniques processes – Fluid Guided & Shape Fitting Guided self-assembly, with more emphasis placed on the latter. The principle of these techniques is based on nature‟s need for lowest energy state of all matter.
The purpose of these techniques is to overcome the problem of stiction during assembly of thin chips sized 3 mm x 3 mm x 50 μm.
Fluid Guided self-assembly will discuss mainly on the processes studied and experiments carried out to create a suitable environment for self-assembly to take place.
Shape Fitting Guided self-assembly process parameters used will be discussed in details in this report, with further analysis being done on individual parameters affecting the yield and chosen to suit the objective of the project. The repeatability of Shape Fitting self-assembly technique is shown by on average to be more than 97% yield within 5 minutes.
The self-assembled chips will then be gang bonded to a substrate by thermo-compression. Analysis was done to improve various process parameters after gang bonding to increase the overall yield of self-assembly. The highest yield obtained for gang bonding is about 87%.
Shape Fitting Guided self-assembly technique is a promising and inexpensive solution for assembly of thin chips. However process parameters need to be further tuned to make this process suitable for mass manufacturing in the industry. |
| first_indexed | 2024-10-01T04:49:51Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/44421 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:49:51Z |
| publishDate | 2011 |
| record_format | dspace |
| spelling | ntu-10356/444212023-03-04T15:37:31Z Parallel assembly technique for thin chip using guided self-assembly Lee, Ming Kian. Gan Chee Lip School of Materials Science and Engineering A*STAR Institute of Microelectronics DRNTU::Engineering This report covers two parallel self-assembly techniques processes – Fluid Guided & Shape Fitting Guided self-assembly, with more emphasis placed on the latter. The principle of these techniques is based on nature‟s need for lowest energy state of all matter. The purpose of these techniques is to overcome the problem of stiction during assembly of thin chips sized 3 mm x 3 mm x 50 μm. Fluid Guided self-assembly will discuss mainly on the processes studied and experiments carried out to create a suitable environment for self-assembly to take place. Shape Fitting Guided self-assembly process parameters used will be discussed in details in this report, with further analysis being done on individual parameters affecting the yield and chosen to suit the objective of the project. The repeatability of Shape Fitting self-assembly technique is shown by on average to be more than 97% yield within 5 minutes. The self-assembled chips will then be gang bonded to a substrate by thermo-compression. Analysis was done to improve various process parameters after gang bonding to increase the overall yield of self-assembly. The highest yield obtained for gang bonding is about 87%. Shape Fitting Guided self-assembly technique is a promising and inexpensive solution for assembly of thin chips. However process parameters need to be further tuned to make this process suitable for mass manufacturing in the industry. Bachelor of Engineering (Materials Engineering) 2011-06-01T07:09:35Z 2011-06-01T07:09:35Z 2011 2011 Final Year Project (FYP) http://hdl.handle.net/10356/44421 en Nanyang Technological University 56 p. application/pdf |
| spellingShingle | DRNTU::Engineering Lee, Ming Kian. Parallel assembly technique for thin chip using guided self-assembly |
| title | Parallel assembly technique for thin chip using guided self-assembly |
| title_full | Parallel assembly technique for thin chip using guided self-assembly |
| title_fullStr | Parallel assembly technique for thin chip using guided self-assembly |
| title_full_unstemmed | Parallel assembly technique for thin chip using guided self-assembly |
| title_short | Parallel assembly technique for thin chip using guided self-assembly |
| title_sort | parallel assembly technique for thin chip using guided self assembly |
| topic | DRNTU::Engineering |
| url | http://hdl.handle.net/10356/44421 |
| work_keys_str_mv | AT leemingkian parallelassemblytechniqueforthinchipusingguidedselfassembly |