Self-timed CMOS circuits
In this dissertation, three 8-bit differential logic circuits are designed using self-timed technique. These logic circuits have been implemented with 8-bit Ripple Carry adder using the TSMC .25 um process technology. All the three circuits are simulated using HSpice. Then, the performance of the ci...
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| Format: | Thesis |
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2008
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| Online Access: | http://hdl.handle.net/10356/4552 |
| Summary: | In this dissertation, three 8-bit differential logic circuits are designed using self-timed technique. These logic circuits have been implemented with 8-bit Ripple Carry adder using the TSMC .25 um process technology. All the three circuits are simulated using HSpice. Then, the performance of the circuits are compared by measuring the average power dissipation. These circuits are compared using the HSpice simulated results using the HSpice. The differential logic circuits used are Differential Cascode Voltage Switch Logic(DCVSL), Enable/Disable CMOS Differential Circuits(ECDL) and Improved Differential Cascode Voltage Switch Logic(IDCVSL). |
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