Self-timed CMOS circuits
In this dissertation, three 8-bit differential logic circuits are designed using self-timed technique. These logic circuits have been implemented with 8-bit Ripple Carry adder using the TSMC .25 um process technology. All the three circuits are simulated using HSpice. Then, the performance of the ci...
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| Format: | Thesis |
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2008
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| Online Access: | http://hdl.handle.net/10356/4552 |
| _version_ | 1811686006232973312 |
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| author | Lakshminarayanan Srinivasan |
| author2 | Lau, Kim Teen |
| author_facet | Lau, Kim Teen Lakshminarayanan Srinivasan |
| author_sort | Lakshminarayanan Srinivasan |
| collection | NTU |
| description | In this dissertation, three 8-bit differential logic circuits are designed using self-timed technique. These logic circuits have been implemented with 8-bit Ripple Carry adder using the TSMC .25 um process technology. All the three circuits are simulated using HSpice. Then, the performance of the circuits are compared by measuring the average power dissipation. These circuits are compared using the HSpice simulated results using the HSpice. The differential logic circuits used are Differential Cascode Voltage Switch Logic(DCVSL), Enable/Disable CMOS Differential Circuits(ECDL) and Improved Differential Cascode Voltage Switch Logic(IDCVSL). |
| first_indexed | 2024-10-01T04:53:33Z |
| format | Thesis |
| id | ntu-10356/4552 |
| institution | Nanyang Technological University |
| last_indexed | 2024-10-01T04:53:33Z |
| publishDate | 2008 |
| record_format | dspace |
| spelling | ntu-10356/45522023-07-04T15:57:47Z Self-timed CMOS circuits Lakshminarayanan Srinivasan Lau, Kim Teen School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits In this dissertation, three 8-bit differential logic circuits are designed using self-timed technique. These logic circuits have been implemented with 8-bit Ripple Carry adder using the TSMC .25 um process technology. All the three circuits are simulated using HSpice. Then, the performance of the circuits are compared by measuring the average power dissipation. These circuits are compared using the HSpice simulated results using the HSpice. The differential logic circuits used are Differential Cascode Voltage Switch Logic(DCVSL), Enable/Disable CMOS Differential Circuits(ECDL) and Improved Differential Cascode Voltage Switch Logic(IDCVSL). Master of Science (Consumer Electronics) 2008-09-17T09:54:05Z 2008-09-17T09:54:05Z 2006 2006 Thesis http://hdl.handle.net/10356/4552 Nanyang Technological University application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Lakshminarayanan Srinivasan Self-timed CMOS circuits |
| title | Self-timed CMOS circuits |
| title_full | Self-timed CMOS circuits |
| title_fullStr | Self-timed CMOS circuits |
| title_full_unstemmed | Self-timed CMOS circuits |
| title_short | Self-timed CMOS circuits |
| title_sort | self timed cmos circuits |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits |
| url | http://hdl.handle.net/10356/4552 |
| work_keys_str_mv | AT lakshminarayanansrinivasan selftimedcmoscircuits |