Error-tolerant multiplier for high speed application
With the advent of hand held computing devices that require functionality rivaling the desktop, low-power and high-performance systems have become very important. The transistor network contributes mostly to the overall power dissipation and is becoming a major obstacle in implementing those systems...
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| Other Authors: | |
| Format: | Thesis |
| Language: | English |
| Published: |
2011
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| Online Access: | https://hdl.handle.net/10356/45661 |
| _version_ | 1826118588421898240 |
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| author | Khaing, Yin Kyaw |
| author2 | Yeo Kiat Seng |
| author_facet | Yeo Kiat Seng Khaing, Yin Kyaw |
| author_sort | Khaing, Yin Kyaw |
| collection | NTU |
| description | With the advent of hand held computing devices that require functionality rivaling the desktop, low-power and high-performance systems have become very important. The transistor network contributes mostly to the overall power dissipation and is becoming a major obstacle in implementing those systems. Hence, the need for high performance basic sequential element with low-power dissipation is steadily growing. The aim of this project is to develop a new type of multiplier to fulfill this need. In this report, for the first time, a multiplier design concept that engages accuracy as a design parameter is proposed. By introducing accuracy as a design parameter, we can break-through the bottleneck of conventional digital IC design techniques to improve on the performances of power consumption and speed. The two dimensional trade-off between power and speed becomes three-dimensional, i.e. power-speed-accuracy. To realize the design concept, digital multiplier circuits were studied and a novel mechanism is proposed in this work. The new type of multiplier adopting the proposed mechanism is named Error-Tolerant Multiplier (also called ETM). As illustration, the designs of 8-bit and 12-bit Error-Tolerant Multiplier, taken as examples, are described to elaborate on the design process and detailed circuit implementation of an ETM. |
| first_indexed | 2024-10-01T04:46:15Z |
| format | Thesis |
| id | ntu-10356/45661 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:46:15Z |
| publishDate | 2011 |
| record_format | dspace |
| spelling | ntu-10356/456612023-07-04T17:07:07Z Error-tolerant multiplier for high speed application Khaing, Yin Kyaw Yeo Kiat Seng Goh Wang Ling School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits With the advent of hand held computing devices that require functionality rivaling the desktop, low-power and high-performance systems have become very important. The transistor network contributes mostly to the overall power dissipation and is becoming a major obstacle in implementing those systems. Hence, the need for high performance basic sequential element with low-power dissipation is steadily growing. The aim of this project is to develop a new type of multiplier to fulfill this need. In this report, for the first time, a multiplier design concept that engages accuracy as a design parameter is proposed. By introducing accuracy as a design parameter, we can break-through the bottleneck of conventional digital IC design techniques to improve on the performances of power consumption and speed. The two dimensional trade-off between power and speed becomes three-dimensional, i.e. power-speed-accuracy. To realize the design concept, digital multiplier circuits were studied and a novel mechanism is proposed in this work. The new type of multiplier adopting the proposed mechanism is named Error-Tolerant Multiplier (also called ETM). As illustration, the designs of 8-bit and 12-bit Error-Tolerant Multiplier, taken as examples, are described to elaborate on the design process and detailed circuit implementation of an ETM. MASTER OF ENGINEERING (EEE) 2011-06-16T01:37:27Z 2011-06-16T01:37:27Z 2011 2011 Thesis Khaing, Y. K. (2011). Error-tolerant multiplier for high speed application. Master’s thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/45661 10.32657/10356/45661 en 107 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Khaing, Yin Kyaw Error-tolerant multiplier for high speed application |
| title | Error-tolerant multiplier for high speed application |
| title_full | Error-tolerant multiplier for high speed application |
| title_fullStr | Error-tolerant multiplier for high speed application |
| title_full_unstemmed | Error-tolerant multiplier for high speed application |
| title_short | Error-tolerant multiplier for high speed application |
| title_sort | error tolerant multiplier for high speed application |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits |
| url | https://hdl.handle.net/10356/45661 |
| work_keys_str_mv | AT khaingyinkyaw errortolerantmultiplierforhighspeedapplication |