Design of a low-voltage CMOS analogue multiplier
The objective of this project is to design a low-voltage analogue multiplier operating on a 1.3V voltage supply and its' 3-dB bandwidth is expected to be about 100 KHz. This multiplier should be able to operate with the input signals of the 1.2V voltage swing and expect an output voltage swing...
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| Format: | Thesis |
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2008
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| Online Access: | http://hdl.handle.net/10356/4598 |