Network-on-chip based manycore systems
As deep sub-micron technologies advance, architectures of microprocessors have evolved from traditional monolithic ones into parallel ones which consist of large number of small but energy efficient cores that rely on Network-on-Chip (NoC) communication infrastructure to achieve scalability. This th...
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| Format: | Thesis |
| Language: | English |
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2011
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| Online Access: | https://hdl.handle.net/10356/46287 |
| _version_ | 1826110471721189376 |
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| author | Liao, Xiongfei |
| author2 | Thambipillai Srikanthan |
| author_facet | Thambipillai Srikanthan Liao, Xiongfei |
| author_sort | Liao, Xiongfei |
| collection | NTU |
| description | As deep sub-micron technologies advance, architectures of microprocessors have evolved from traditional monolithic ones into parallel ones which consist of large number of small but energy efficient cores that rely on Network-on-Chip (NoC) communication infrastructure to achieve scalability. This thesis presents the design and development of a comprehensive simulation framework for an NoC based system simulator covering all system levels from low-level hardware modules to high-level software applications. The motivation stems from the fact that there exists no publicly available simulator that supports embedded NoC based manycore systems. A cycle-level simulation framework has been proposed using the UNISIM environment to complement the configurable on-chip network built upon efficient pipelined routers that employ wormhole switching and virtual-channel flow control. In order to accelerate the cycle-level micro-architectural simulations for manycore systems, novel techniques have been devised to accelerate the cycle-level simulations on multi-core platforms. In particular, we have exploited the fine-grained parallelism within each simulated cycle using Pthreads, leading to notable speedups. The proposed multithreaded simulation engine exploits inherent parallelism with the help of an adaptive technique for managing the computation workload and relies on a graph partitioning based technique for automating load balancing among workloads of multithreaded executions. Our investigations show that, by adaptive distribution of modules among multiple CPU cores of the simulation platform at runtime, the proposed techniques can provide for up to 6X speed up using an 8-core computer. Existing allocation strategies do not lend well NoC based many-core systems when their core counts increase. In this thesis, a runtime resource management strategy has been proposed to overcome these limitations thereby making it suitable for NoC based manycore systems that must support a large number of cores. The proposed resource management strategy relies on submesh based scheme for organizing resources at runtime allocation/deallocation process. It employs a hierarchical-based resource allocation and deallocation scheme to speed-up and to save energy. |
| first_indexed | 2024-10-01T02:34:58Z |
| format | Thesis |
| id | ntu-10356/46287 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T02:34:58Z |
| publishDate | 2011 |
| record_format | dspace |
| spelling | ntu-10356/462872023-03-04T00:47:53Z Network-on-chip based manycore systems Liao, Xiongfei Thambipillai Srikanthan School of Computer Engineering Centre for High Performance Embedded Systems DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures As deep sub-micron technologies advance, architectures of microprocessors have evolved from traditional monolithic ones into parallel ones which consist of large number of small but energy efficient cores that rely on Network-on-Chip (NoC) communication infrastructure to achieve scalability. This thesis presents the design and development of a comprehensive simulation framework for an NoC based system simulator covering all system levels from low-level hardware modules to high-level software applications. The motivation stems from the fact that there exists no publicly available simulator that supports embedded NoC based manycore systems. A cycle-level simulation framework has been proposed using the UNISIM environment to complement the configurable on-chip network built upon efficient pipelined routers that employ wormhole switching and virtual-channel flow control. In order to accelerate the cycle-level micro-architectural simulations for manycore systems, novel techniques have been devised to accelerate the cycle-level simulations on multi-core platforms. In particular, we have exploited the fine-grained parallelism within each simulated cycle using Pthreads, leading to notable speedups. The proposed multithreaded simulation engine exploits inherent parallelism with the help of an adaptive technique for managing the computation workload and relies on a graph partitioning based technique for automating load balancing among workloads of multithreaded executions. Our investigations show that, by adaptive distribution of modules among multiple CPU cores of the simulation platform at runtime, the proposed techniques can provide for up to 6X speed up using an 8-core computer. Existing allocation strategies do not lend well NoC based many-core systems when their core counts increase. In this thesis, a runtime resource management strategy has been proposed to overcome these limitations thereby making it suitable for NoC based manycore systems that must support a large number of cores. The proposed resource management strategy relies on submesh based scheme for organizing resources at runtime allocation/deallocation process. It employs a hierarchical-based resource allocation and deallocation scheme to speed-up and to save energy. DOCTOR OF PHILOSOPHY (SCE) 2011-11-28T08:13:10Z 2011-11-28T08:13:10Z 2011 2011 Thesis Liao, X. F. (2011). Network-on-chip based manycore systems. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/46287 10.32657/10356/46287 en 227 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures Liao, Xiongfei Network-on-chip based manycore systems |
| title | Network-on-chip based manycore systems |
| title_full | Network-on-chip based manycore systems |
| title_fullStr | Network-on-chip based manycore systems |
| title_full_unstemmed | Network-on-chip based manycore systems |
| title_short | Network-on-chip based manycore systems |
| title_sort | network on chip based manycore systems |
| topic | DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures |
| url | https://hdl.handle.net/10356/46287 |
| work_keys_str_mv | AT liaoxiongfei networkonchipbasedmanycoresystems |