ASIC implementation of a video decoder
As digital signal processors have optimized instruction sets to manage the required operations so image and video codec is implemented mainly in software. Improvements in speed occur primarily because the hardware can be tailored to the compression algorithm as well as the application Using ASIC/FPG...
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| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2011
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| Online Access: | http://hdl.handle.net/10356/46536 |
| _version_ | 1811685361543282688 |
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| author | Dang Bao Duc |
| author2 | Ho Duan Juat |
| author_facet | Ho Duan Juat Dang Bao Duc |
| author_sort | Dang Bao Duc |
| collection | NTU |
| description | As digital signal processors have optimized instruction sets to manage the required operations so image and video codec is implemented mainly in software. Improvements in speed occur primarily because the hardware can be tailored to the compression algorithm as well as the application Using ASIC/FPGA device to implement a codec increased processing speed due to the use of customized hardware. The JPEG algorithm was chosen for this project because it is ordinarily used in many multimedia applications, and is an important standard for video compression today. The JPEG includes many compression techniques such as variable length coding, discrete cosine transform, quantization…. Variable length coding (VLC) reduces data redundancy based on assigning short codeword to frequent symbols and long codeword to infrequent symbols. In the design of VLC decoder (VLD), the most important objective is to achieve high throughput. Many algorithms and architectures of VLD have been proposed. This project will be focus on Constant output rate decoder for VLD. The simulations of the model show that the design proposed in this thesis can meet the real time requirement for HD video decoding |
| first_indexed | 2024-10-01T04:43:18Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/46536 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:43:18Z |
| publishDate | 2011 |
| record_format | dspace |
| spelling | ntu-10356/465362023-07-07T15:49:47Z ASIC implementation of a video decoder Dang Bao Duc Ho Duan Juat School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits As digital signal processors have optimized instruction sets to manage the required operations so image and video codec is implemented mainly in software. Improvements in speed occur primarily because the hardware can be tailored to the compression algorithm as well as the application Using ASIC/FPGA device to implement a codec increased processing speed due to the use of customized hardware. The JPEG algorithm was chosen for this project because it is ordinarily used in many multimedia applications, and is an important standard for video compression today. The JPEG includes many compression techniques such as variable length coding, discrete cosine transform, quantization…. Variable length coding (VLC) reduces data redundancy based on assigning short codeword to frequent symbols and long codeword to infrequent symbols. In the design of VLC decoder (VLD), the most important objective is to achieve high throughput. Many algorithms and architectures of VLD have been proposed. This project will be focus on Constant output rate decoder for VLD. The simulations of the model show that the design proposed in this thesis can meet the real time requirement for HD video decoding Bachelor of Engineering 2011-12-15T03:41:24Z 2011-12-15T03:41:24Z 2011 2011 Final Year Project (FYP) http://hdl.handle.net/10356/46536 en Nanyang Technological University 70 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Dang Bao Duc ASIC implementation of a video decoder |
| title | ASIC implementation of a video decoder |
| title_full | ASIC implementation of a video decoder |
| title_fullStr | ASIC implementation of a video decoder |
| title_full_unstemmed | ASIC implementation of a video decoder |
| title_short | ASIC implementation of a video decoder |
| title_sort | asic implementation of a video decoder |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits |
| url | http://hdl.handle.net/10356/46536 |
| work_keys_str_mv | AT dangbaoduc asicimplementationofavideodecoder |