Electrical modeling of through-silicon-via for 3D integrated circuits
117 p.
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| Formato: | Tesis |
| Publicado: |
2011
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| Acceso en línea: | http://hdl.handle.net/10356/46790 |
| _version_ | 1826119119722774528 |
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| author | Santhosh Onkaraiah. |
| author2 | Tan Chuan Seng |
| author_facet | Tan Chuan Seng Santhosh Onkaraiah. |
| author_sort | Santhosh Onkaraiah. |
| collection | NTU |
| description | 117 p. |
| first_indexed | 2024-10-01T04:54:50Z |
| format | Thesis |
| id | ntu-10356/46790 |
| institution | Nanyang Technological University |
| last_indexed | 2024-10-01T04:54:50Z |
| publishDate | 2011 |
| record_format | dspace |
| spelling | ntu-10356/467902023-07-04T15:02:16Z Electrical modeling of through-silicon-via for 3D integrated circuits Santhosh Onkaraiah. Tan Chuan Seng School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits 117 p. Increased use of technology in day to day life for seamless activity and increased living comforts have been driving the Integrated Circuit (IC) industry to produce better hardware at cheaper and faster rate. Hence Ultra Large Scale Integration (ULSI) of ICs is accelerating to account for the need of high speed systems. Traditional scaling alone is believed to be insufficient to satisfy the interconnect performance going forward. Hence equivalent scaling using unconventional approaches would be necessary. As the scaling of integrated circuits to achieve faster, denser and smaller devices continues to drive the industry, we are at the juncture where many hurdles need to be addressed to continue on this remarkable journey of semiconductors. International Technology Roadmap for Semiconductors [ITRS] projects that the device delay is continuously scaling down but interconnect delays are increasing at a rapid rate for global and semi global interconnects Master of Science (Electronics) 2011-12-23T09:53:52Z 2011-12-23T09:53:52Z 2011 Thesis http://hdl.handle.net/10356/46790 Nanyang Technological University application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Santhosh Onkaraiah. Electrical modeling of through-silicon-via for 3D integrated circuits |
| title | Electrical modeling of through-silicon-via for 3D integrated circuits |
| title_full | Electrical modeling of through-silicon-via for 3D integrated circuits |
| title_fullStr | Electrical modeling of through-silicon-via for 3D integrated circuits |
| title_full_unstemmed | Electrical modeling of through-silicon-via for 3D integrated circuits |
| title_short | Electrical modeling of through-silicon-via for 3D integrated circuits |
| title_sort | electrical modeling of through silicon via for 3d integrated circuits |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
| url | http://hdl.handle.net/10356/46790 |
| work_keys_str_mv | AT santhoshonkaraiah electricalmodelingofthroughsiliconviafor3dintegratedcircuits |