Customizable instruction cache hierarchy for embedded systems
146 p.
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| Other Authors: | |
| Format: | Thesis |
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2011
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| Online Access: | https://hdl.handle.net/10356/47483 |
| _version_ | 1811691908480630784 |
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| author | Kugan Vivekanandarajah |
| author2 | Thambipillai Srikanthan |
| author_facet | Thambipillai Srikanthan Kugan Vivekanandarajah |
| author_sort | Kugan Vivekanandarajah |
| collection | NTU |
| description | 146 p. |
| first_indexed | 2024-10-01T06:27:22Z |
| format | Thesis |
| id | ntu-10356/47483 |
| institution | Nanyang Technological University |
| last_indexed | 2024-10-01T06:27:22Z |
| publishDate | 2011 |
| record_format | dspace |
| spelling | ntu-10356/474832023-03-04T00:41:15Z Customizable instruction cache hierarchy for embedded systems Kugan Vivekanandarajah Thambipillai Srikanthan School of Computer Engineering DRNTU::Engineering::Computer science and engineering::Hardware::Memory structures 146 p. Cache hierarchy bridges the ever increasing performance gap between the fast processing core and slow main memory. In an effort to improve the total system performance, the high performance microprocessor designers commit more and more transistor budget for cache memory systems. As a result, power consumption of cache memory subsystems has been increasing notably over each processor generation. Although a number of cache optimization techniques to reduce power consumption have been reported in the literature, power consumption in cache memories is a major concern and accounts for as much as 50% of the total processor power. Since the instruction cache consumes the majority of this power, predictor based schemes have been proposed for the instruction cache hierarchy in an attempt to provide for an overall reduction in the energy delay product. DOCTOR OF PHILOSOPHY (SCE) 2011-12-27T08:25:54Z 2011-12-27T08:25:54Z 2005 2005 Thesis Kugan, V. (2005). Customizable instruction cache hierarchy for embedded systems. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/47483 10.32657/10356/47483 Nanyang Technological University application/pdf |
| spellingShingle | DRNTU::Engineering::Computer science and engineering::Hardware::Memory structures Kugan Vivekanandarajah Customizable instruction cache hierarchy for embedded systems |
| title | Customizable instruction cache hierarchy for embedded systems |
| title_full | Customizable instruction cache hierarchy for embedded systems |
| title_fullStr | Customizable instruction cache hierarchy for embedded systems |
| title_full_unstemmed | Customizable instruction cache hierarchy for embedded systems |
| title_short | Customizable instruction cache hierarchy for embedded systems |
| title_sort | customizable instruction cache hierarchy for embedded systems |
| topic | DRNTU::Engineering::Computer science and engineering::Hardware::Memory structures |
| url | https://hdl.handle.net/10356/47483 |
| work_keys_str_mv | AT kuganvivekanandarajah customizableinstructioncachehierarchyforembeddedsystems |