| Summary: | Emerging communication paradigms like opportunistic spectrum access and wireless heterogeneous networks impose a high degree of flexibility on the underlying physical layer hardware of the mobile terminal. A software implementation of the radio baseband algorithms on an instruction set architecture (ISA) offers the highest degree of flexibility and hardware reusability, since the reconfiguration of the terminal for a new standard involves a mere change of software code. However the power efficiencies of ISAs have not scaled to the point where the entire baseband computations of a mobile handset can be performed in software. The computationally intensive signal processing tasks in the radio baseband have to be accelerated in hardware. Dedicated hardware (HW) accelerator cores have a power efficiency which is several orders higher than a software implementation and hence, have been extensively used for accelerating the computationally intensive tasks like channelization and decoding. HW accelerators, however, are inflexible in general and are optimized for a single specification. Incorporating flexibility necessarily incurs both an area and power penalty. The growing need for supporting multiple wireless standards with heterogeneous throughput and mobility requirements in a small form factor mobile handset with a limited silicon area requires the accelerator cores to be flexible and reusable in addition to being power efficient.
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