ASIC implementation of a high speed data scaler for residue number system
Unconventional number system, the Residue Number System (RNS) is introduced for its efficient arithmetic operations such as addition, subtraction and multiplication as long operations are broken down into several shorter and independent operations without carry propagation between them. How...
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| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2012
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| Online Access: | http://hdl.handle.net/10356/49912 |
| _version_ | 1826128412889055232 |
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| author | Chay, Chien Hong. |
| author2 | Chang Chip Hong |
| author_facet | Chang Chip Hong Chay, Chien Hong. |
| author_sort | Chay, Chien Hong. |
| collection | NTU |
| description | Unconventional number system, the Residue Number System (RNS) is introduced
for its efficient arithmetic operations such as addition, subtraction and multiplication
as long operations are broken down into several shorter and independent operations
without carry propagation between them. However, scaling, an essential operation in
digital signal processing remained as one of the bottleneck of RNS which hinder the
wider adoption of RNS due to its non-weighted characteristic.In this project, the architecture of the new proposed scaling algorithm for the
programmable scaler is coded and synthesized. The placement and routing of this
new RNS design, combining with other designs is also performed using the
Cadence® SoC Encounter™ RTL-to-GDSII System version 8.1. Lastly, testing
circuitry is also developed to test the functionality of the chip after being fabricated. |
| first_indexed | 2024-10-01T07:24:32Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/49912 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T07:24:32Z |
| publishDate | 2012 |
| record_format | dspace |
| spelling | ntu-10356/499122023-07-07T16:45:30Z ASIC implementation of a high speed data scaler for residue number system Chay, Chien Hong. Chang Chip Hong School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Unconventional number system, the Residue Number System (RNS) is introduced for its efficient arithmetic operations such as addition, subtraction and multiplication as long operations are broken down into several shorter and independent operations without carry propagation between them. However, scaling, an essential operation in digital signal processing remained as one of the bottleneck of RNS which hinder the wider adoption of RNS due to its non-weighted characteristic.In this project, the architecture of the new proposed scaling algorithm for the programmable scaler is coded and synthesized. The placement and routing of this new RNS design, combining with other designs is also performed using the Cadence® SoC Encounter™ RTL-to-GDSII System version 8.1. Lastly, testing circuitry is also developed to test the functionality of the chip after being fabricated. Bachelor of Engineering 2012-05-25T06:29:38Z 2012-05-25T06:29:38Z 2012 2012 Final Year Project (FYP) http://hdl.handle.net/10356/49912 en Nanyang Technological University 98 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Chay, Chien Hong. ASIC implementation of a high speed data scaler for residue number system |
| title | ASIC implementation of a high speed data scaler for residue number system |
| title_full | ASIC implementation of a high speed data scaler for residue number system |
| title_fullStr | ASIC implementation of a high speed data scaler for residue number system |
| title_full_unstemmed | ASIC implementation of a high speed data scaler for residue number system |
| title_short | ASIC implementation of a high speed data scaler for residue number system |
| title_sort | asic implementation of a high speed data scaler for residue number system |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
| url | http://hdl.handle.net/10356/49912 |
| work_keys_str_mv | AT chaychienhong asicimplementationofahighspeeddatascalerforresiduenumbersystem |