Low-power and robust SRAM design
This thesis pertains to the design of low power and robust SRAMs without significant area overhead and speed penalty. Novel designs are presented to reduce the power dissipation by using dynamic voltage scaling as well as reducing the power dissipation on large capacitive metal lines, for example bi...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis |
| Language: | English |
| Published: |
2013
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/51690 |
| _version_ | 1826124359652081664 |
|---|---|
| author | Chen, Junchao. |
| author2 | Gwee Bah Hwee |
| author_facet | Gwee Bah Hwee Chen, Junchao. |
| author_sort | Chen, Junchao. |
| collection | NTU |
| description | This thesis pertains to the design of low power and robust SRAMs without significant area overhead and speed penalty. Novel designs are presented to reduce the power dissipation by using dynamic voltage scaling as well as reducing the power dissipation on large capacitive metal lines, for example bitlines. Robustness is enhanced by using asynchronous Quasi-Delay-Insensitive (QDI) technique to reduce the possible synchronous failure in conventional synchronous counterpart, by using novel memory cells to reduce the read and write stability problem in conventional SRAMs as well as by using efficient bit-interleaved structure to increase the soft-error immunity when combined with error correction code (ECC). |
| first_indexed | 2024-10-01T06:19:02Z |
| format | Thesis |
| id | ntu-10356/51690 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:19:02Z |
| publishDate | 2013 |
| record_format | dspace |
| spelling | ntu-10356/516902023-07-04T16:08:10Z Low-power and robust SRAM design Chen, Junchao. Gwee Bah Hwee School of Electrical and Electronic Engineering Centre for Integrated Circuits and Systems DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits This thesis pertains to the design of low power and robust SRAMs without significant area overhead and speed penalty. Novel designs are presented to reduce the power dissipation by using dynamic voltage scaling as well as reducing the power dissipation on large capacitive metal lines, for example bitlines. Robustness is enhanced by using asynchronous Quasi-Delay-Insensitive (QDI) technique to reduce the possible synchronous failure in conventional synchronous counterpart, by using novel memory cells to reduce the read and write stability problem in conventional SRAMs as well as by using efficient bit-interleaved structure to increase the soft-error immunity when combined with error correction code (ECC). Master of Engineering 2013-04-08T07:46:34Z 2013-04-08T07:46:34Z 2013 2013 Thesis http://hdl.handle.net/10356/51690 en 77 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Chen, Junchao. Low-power and robust SRAM design |
| title | Low-power and robust SRAM design |
| title_full | Low-power and robust SRAM design |
| title_fullStr | Low-power and robust SRAM design |
| title_full_unstemmed | Low-power and robust SRAM design |
| title_short | Low-power and robust SRAM design |
| title_sort | low power and robust sram design |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
| url | http://hdl.handle.net/10356/51690 |
| work_keys_str_mv | AT chenjunchao lowpowerandrobustsramdesign |