Characterization of semiconductor process parameters
Silicon, being the most mature technology in the electronics industry, is facing limitations and challenges that threaten to displace Moore’s Law as device sizes get increasingly smaller. The monolithic integration of III-V to Silicon via wafer bonding will marry the advantages of both platforms for...
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| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
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2013
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| Online Access: | http://hdl.handle.net/10356/53005 |
| _version_ | 1826127708929654784 |
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| author | Gan, Chin Ngap |
| author2 | Yoon Soon Fatt |
| author_facet | Yoon Soon Fatt Gan, Chin Ngap |
| author_sort | Gan, Chin Ngap |
| collection | NTU |
| description | Silicon, being the most mature technology in the electronics industry, is facing limitations and challenges that threaten to displace Moore’s Law as device sizes get increasingly smaller. The monolithic integration of III-V to Silicon via wafer bonding will marry the advantages of both platforms for the realization of optoelectronic integrated circuits. However, due to the severe thermal expansion mismatch, high temperature processes cannot be performed on thick, industrial scale size wafer. In this study, 2 inch Silicon bonded to Gallium-Arsenide wafers using the plasma activated direct wafer bonding technique is chemical-mechanical polished on the GaAs backside and was able to reach to an average thickness of 60µm. Thinning rate of 4µm/min and surface roughness of 1.5~1.6nm were achieved through the current efforts. Through this study, a pair of thinned down Si to GaAs bonded sample can go through high temperature molecular beam epitaxy process for device structure growth. |
| first_indexed | 2024-10-01T07:13:17Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/53005 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T07:13:17Z |
| publishDate | 2013 |
| record_format | dspace |
| spelling | ntu-10356/530052023-07-07T16:40:57Z Characterization of semiconductor process parameters Gan, Chin Ngap Yoon Soon Fatt School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Microelectronics DRNTU::Engineering::Materials::Material testing and characterization DRNTU::Engineering::Electrical and electronic engineering::Semiconductors Silicon, being the most mature technology in the electronics industry, is facing limitations and challenges that threaten to displace Moore’s Law as device sizes get increasingly smaller. The monolithic integration of III-V to Silicon via wafer bonding will marry the advantages of both platforms for the realization of optoelectronic integrated circuits. However, due to the severe thermal expansion mismatch, high temperature processes cannot be performed on thick, industrial scale size wafer. In this study, 2 inch Silicon bonded to Gallium-Arsenide wafers using the plasma activated direct wafer bonding technique is chemical-mechanical polished on the GaAs backside and was able to reach to an average thickness of 60µm. Thinning rate of 4µm/min and surface roughness of 1.5~1.6nm were achieved through the current efforts. Through this study, a pair of thinned down Si to GaAs bonded sample can go through high temperature molecular beam epitaxy process for device structure growth. Bachelor of Engineering 2013-05-29T07:21:19Z 2013-05-29T07:21:19Z 2013 2013 Final Year Project (FYP) http://hdl.handle.net/10356/53005 en Nanyang Technological University 56 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Microelectronics DRNTU::Engineering::Materials::Material testing and characterization DRNTU::Engineering::Electrical and electronic engineering::Semiconductors Gan, Chin Ngap Characterization of semiconductor process parameters |
| title | Characterization of semiconductor process parameters |
| title_full | Characterization of semiconductor process parameters |
| title_fullStr | Characterization of semiconductor process parameters |
| title_full_unstemmed | Characterization of semiconductor process parameters |
| title_short | Characterization of semiconductor process parameters |
| title_sort | characterization of semiconductor process parameters |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Microelectronics DRNTU::Engineering::Materials::Material testing and characterization DRNTU::Engineering::Electrical and electronic engineering::Semiconductors |
| url | http://hdl.handle.net/10356/53005 |
| work_keys_str_mv | AT ganchinngap characterizationofsemiconductorprocessparameters |