Wafer-level fine pitch Cu-Cu bonding for 3-D stacking of integrated circuits
The increasing demand for system performance enhancement and more functionality has led to the exploration of 3-D IC technology, which possesses attractive benefits in form factor, density, performance, heterogeneous integration, and lower cost. One of the key challenges to realize 3-D integration i...
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| Other Authors: | |
| Format: | Thesis |
| Language: | English |
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2013
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| Online Access: | https://hdl.handle.net/10356/53452 |
| _version_ | 1811681217822588928 |
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| author | Peng, Lan |
| author2 | Lo Guo-Qiang, Patrick |
| author_facet | Lo Guo-Qiang, Patrick Peng, Lan |
| author_sort | Peng, Lan |
| collection | NTU |
| description | The increasing demand for system performance enhancement and more functionality has led to the exploration of 3-D IC technology, which possesses attractive benefits in form factor, density, performance, heterogeneous integration, and lower cost. One of the key challenges to realize 3-D integration is to develop a robust bonding technique. While solder-based technology appears to be a convenient way (since it is widely used in the packaging community) for 3-D stacking, it is inadequate to meet the increasing needs for fine pitch and reliable vertical interconnection in stacked ICs. Among various emerging bonding methods, Cu-Cu bonding is an attractive option because it is able to provide strong mechanical strength to support stacked layers and conduct current effectively with its intrinsic bonding medium. In addition, wafer-to-wafer (W2W) bonding scheme is gaining favorable attention for the feature of higher manufacturing throughput than chip-to-wafer or chip-to-chip. Conventionally, reliable Cu-Cu bond is formed by using thermo-compression bonding (TCB) which makes use of contact pressure and high temperature (> 350 oC) to facilitate inter-diffusion of Cu atoms in order to promote bonding adhesion. However, high temperature TCB process limits its attractiveness due to the stringent thermal budget control of the stacked device. Lowering down the bonding temperature has become extremely difficult due to the ease of Cu surface oxidation which degrades the bonding reliabilities. Therefore, it is important to explore a robust approach to realize high density Cu-Cu bonding at low temperature. This thesis proposes a low temperature wafer-to-wafer fine pitch (5-15 µm) Cu-Cu bonding technology. This technology incorporates bonding enhancement methods such as self-assembled monolayer (SAM) passivation and hermetic Cu seal ring. SAM passivation provides a temporary protection on the Cu surface prior to bonding. It is found to effectively reduce Cu oxidation and particle contamination. The monolayer is also able to be desorbed by thermal annealing process. On the other hand, an introduction of Cu seal ring which can be simultaneous formed during the bonding process exhibits excellent hermetic properties to encapsulate the stacked device. The overall bonding reliability is enhanced with the combination of both two methods. Finally, the applications of SAM and hermetic seal are extended to the practical 3-D integration, where the seamless development of Cu TSV and Cu-Cu bonding are explored in wafer-scale, resulting in promising technology advancement for the future wafer-to-wafer implementation of 3-D ICs. The discussion on Cu-Cu bonding technology in this thesis is divided into the following 4 parts: 1) the fundamental study of thermo-compression Cu-Cu bonding; 2) the development of wafer level fine-pitch Cu-Cu bonding; 3) the characterization of Cu-Cu bonding contact with enhancement methods; 4) the characterization of fine pitch Cu-Cu bonding system and 3-D stacking demonstration of TSV and Cu-Cu bonding integration. |
| first_indexed | 2024-10-01T03:37:26Z |
| format | Thesis |
| id | ntu-10356/53452 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T03:37:26Z |
| publishDate | 2013 |
| record_format | dspace |
| spelling | ntu-10356/534522023-07-04T17:09:51Z Wafer-level fine pitch Cu-Cu bonding for 3-D stacking of integrated circuits Peng, Lan Lo Guo-Qiang, Patrick Li Hong Yu Tan Chuan Seng School of Electrical and Electronic Engineering A*STAR Institute of Microelectronics DRNTU::Engineering::Electrical and electronic engineering The increasing demand for system performance enhancement and more functionality has led to the exploration of 3-D IC technology, which possesses attractive benefits in form factor, density, performance, heterogeneous integration, and lower cost. One of the key challenges to realize 3-D integration is to develop a robust bonding technique. While solder-based technology appears to be a convenient way (since it is widely used in the packaging community) for 3-D stacking, it is inadequate to meet the increasing needs for fine pitch and reliable vertical interconnection in stacked ICs. Among various emerging bonding methods, Cu-Cu bonding is an attractive option because it is able to provide strong mechanical strength to support stacked layers and conduct current effectively with its intrinsic bonding medium. In addition, wafer-to-wafer (W2W) bonding scheme is gaining favorable attention for the feature of higher manufacturing throughput than chip-to-wafer or chip-to-chip. Conventionally, reliable Cu-Cu bond is formed by using thermo-compression bonding (TCB) which makes use of contact pressure and high temperature (> 350 oC) to facilitate inter-diffusion of Cu atoms in order to promote bonding adhesion. However, high temperature TCB process limits its attractiveness due to the stringent thermal budget control of the stacked device. Lowering down the bonding temperature has become extremely difficult due to the ease of Cu surface oxidation which degrades the bonding reliabilities. Therefore, it is important to explore a robust approach to realize high density Cu-Cu bonding at low temperature. This thesis proposes a low temperature wafer-to-wafer fine pitch (5-15 µm) Cu-Cu bonding technology. This technology incorporates bonding enhancement methods such as self-assembled monolayer (SAM) passivation and hermetic Cu seal ring. SAM passivation provides a temporary protection on the Cu surface prior to bonding. It is found to effectively reduce Cu oxidation and particle contamination. The monolayer is also able to be desorbed by thermal annealing process. On the other hand, an introduction of Cu seal ring which can be simultaneous formed during the bonding process exhibits excellent hermetic properties to encapsulate the stacked device. The overall bonding reliability is enhanced with the combination of both two methods. Finally, the applications of SAM and hermetic seal are extended to the practical 3-D integration, where the seamless development of Cu TSV and Cu-Cu bonding are explored in wafer-scale, resulting in promising technology advancement for the future wafer-to-wafer implementation of 3-D ICs. The discussion on Cu-Cu bonding technology in this thesis is divided into the following 4 parts: 1) the fundamental study of thermo-compression Cu-Cu bonding; 2) the development of wafer level fine-pitch Cu-Cu bonding; 3) the characterization of Cu-Cu bonding contact with enhancement methods; 4) the characterization of fine pitch Cu-Cu bonding system and 3-D stacking demonstration of TSV and Cu-Cu bonding integration. DOCTOR OF PHILOSOPHY (EEE) 2013-06-04T02:17:46Z 2013-06-04T02:17:46Z 2012 2012 Thesis Peng, L. (2012). Wafer-level fine pitch Cu-Cu bonding for 3-D stacking of integrated circuits. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/53452 10.32657/10356/53452 en 176 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Peng, Lan Wafer-level fine pitch Cu-Cu bonding for 3-D stacking of integrated circuits |
| title | Wafer-level fine pitch Cu-Cu bonding for 3-D stacking of integrated circuits |
| title_full | Wafer-level fine pitch Cu-Cu bonding for 3-D stacking of integrated circuits |
| title_fullStr | Wafer-level fine pitch Cu-Cu bonding for 3-D stacking of integrated circuits |
| title_full_unstemmed | Wafer-level fine pitch Cu-Cu bonding for 3-D stacking of integrated circuits |
| title_short | Wafer-level fine pitch Cu-Cu bonding for 3-D stacking of integrated circuits |
| title_sort | wafer level fine pitch cu cu bonding for 3 d stacking of integrated circuits |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/53452 |
| work_keys_str_mv | AT penglan waferlevelfinepitchcucubondingfor3dstackingofintegratedcircuits |